Citation :

Sagar Vijay Mhatre, Vinitkumar Jayaprakash Dongre, Sudhakar Mande, "MIRA: Memory-Centric Intelligent Reconfigurable Architecture for LSTM," International Journal of Electrical and Electronics Engineering, vol. 13, no. 5, pp. 127-142, 2026. Crossref, https://doi.org/10.14445/23488379/IJEEE-V13I5P111

Abstract

Accurate and real-time state-of-charge (SoC) estimation is essential for safe and efficient operation of lithium-ion batteries in electric vehicles. Although Long Short-Term Memory (LSTM) networks provide high prediction accuracy, their deployment in embedded battery management systems is limited by computational and resource constraints. This paper presents Memory-Centric Intelligent Reconfigurable Architecture (MIRA), a hardware–software co-designed FPGA-based accelerator for real-time SoC prediction using an optimized LSTM model. The proposed framework integrates feature reduction, sequence modeling, and quantization-aware training with hardware-aware optimizations, including fixed-point representation, activation function approximation, and parallelized matrix multiplication. The accelerator is implemented on a low-cost PYNQ-Z2 platform using near-memory computation and tiling to improve performance and energy efficiency. Experimental results show that the proposed design achieves an inference latency of 0.9536 ms per sample with a throughput of 1048.92 samples/s, significantly outperforming a CPU-based implementation. The system consumes 136 mW and achieves 4.28 GOPS/W. A cost-aware metric, GOPS/W/$, is introduced, with the proposed design achieving 0.0331, outperforming existing accelerators. These results demonstrate an effective balance between accuracy, efficiency, and cost for edge deployment.

Keywords

Edge AI, FPGA Acceleration, LSTM, Memory-Centric Architecture, State-of-Charge Estimation

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