Partitioning of VLSI Circuits on the basis of Standard Genetic Algorithm and Comparative Analysis of Partitioning Algorithms

International Journal of Electrical and Electronics Engineering

© 2022 by SSRG - IJEEE Journal

Volume 9 Issue 12

Year of Publication : 2022

Authors : P. Rajeswari, Theodore S Chandra

10.14445/23488379/IJEEE-V9I12P111

How to Cite?

P. Rajeswari, Theodore S Chandra, "Partitioning of VLSI Circuits on the basis of Standard Genetic Algorithm and Comparative Analysis of Partitioning Algorithms," SSRG International Journal of Electrical and Electronics Engineering, vol. 9,  no. 12, pp. 126-133, 2022. Crossref, https://doi.org/10.14445/23488379/IJEEE-V9I12P111

Abstract:

Circuit segmentation or partitioning is one of the important issues in the VLSI physical design scheme. It appears at certain stages in the VLSI design scheme, such as the logic and physical design schemes. The circuit dividing issue is remarkably difficult. The potential of genetic algorithms has been harnessed to take care of many computationally difficult issues on the grounds that current conventional techniques cannot make the expected forward leaps related to complexity, time, and cost. This paper presents and deals with the issue of segmentation of a circuit using a genetic algorithm. The programme provides a number of vertices that are closely related to each other but exceptionally distinct from other divisions. Minimizing the reduction in VLSI circuit segmentation is the highest priority. Other than this, minimum deductions are also included for upgrading various constraints like power, delay, and area. In any case, due to the continuous advancement of semiconductor advancements, a VLSI chip can contain too many semiconductors, and subsequently, the size of the circuit segmentation issue becomes too large. Large segmentation strategies can certainly affect the presentation and cost of a VLSI chip.

Keywords:

VLSI physical design flow, Circuit partitioning, DYPSO, Genetic Algorithm, Chromosomes.

References:

[1] Y. Yodtean, and P. Chantngarm, “Hybrid Algorithms for Circuit Segmentation,” Proceedings of the IEEE Space Ten Conference, vol. 4, 2004.
[2] G. F. Nan, and M. Q. Lee, “Two Novel Coding Ways for Circuit Segmentation Primarily Based Genetic Algorithms,” Proceedings of the Third IEEE International Conference on Machine Learning, vol. 4, pp. 2182–2188, 2005.
[3] G. C. Sipakoulis, I. Karafyllidis, and A. Thanelakis, “Genetic Segmentation and Placement for VLSI Circuits,” Proceedings of The 6th IEEE International Conference on Electronics, Circuits and Systems, vol. 3, pp. 1647-1650, 1999.
[4] C. J. Augeri, and H. H. Ali, “New Graph-Based Algorithms for Segmentation of VLSI Circuits,” 2004 IEEE International Symposium on Circuits and Systems, pp. V-521-V-524, 2004. Crossref, https://doi.org/10.1109/ISCAS.2004.1329055
[5] A. Cincotti, V. Cuttelo, and M. Pavone, “Graph Segmentation of Genetic Algorithms with OPDX,” Proceedings of the IEEE World Congress on process Intelligence, pp. 402–406, 2002.
[6] Shanavas, Hameem, and R. K. Gnanamurthy, “Evolutionary Algorithmical Approach for VLSI Floorplanning Problem,” International Journal of Computer Theory and Engineering, vol. 1, no. 4, pp. 461-464, 2009.
[7] N. Krasnogor, and J. Smith, “A Tutorial for Competent Memetic Algorithms: Model, Taxonomy, and Design Issues,” IEEE Transactions on Evolutionary Computation, vol. 9, no. 5, pp. 474-488, 2005. Crossref, https://doi.org/10.1109/TEVC.2005.850260
[8] Jianhua Li, and L. Behjat, “A Connectivity Based Clustering Algorithm with Application to VLSI Circuit Partitioning,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 53, no. 5, pp. 384-388, 2006. Crossref, https://doi.org/10.1109/TCSII.2005.862174
[9] N. Selvakkumaran, and G. Karypis, “Multiobjective Hypergraph-Partitioning Algorithms for Cut and Maximum Subdomain-Degree Minimization,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 25, no. 3, pp. 504- 517, 2006. Crossref, https://doi.org/10.1109/TCAD.2005.854637
[10] Roba khega, Kamal Mahmoud Afisa, and Mohammed Yassin Subaih, “Comparison Between the Performance of the Simulated Annealing and Genetic Algorithms in Physical Conductor Orientation within FPGA,” SSRG International Journal of VLSI & Signal Processing, vol. 6, no. 3, pp. 14-17, 2019. Crossref, https://doi.org/10.14445/23942584/IJVSP-V6I3P104
[11] I. H. Shanavas, R. K. Gnanamurthy, and T. S. Thangaraj, “A Novel Approach to Find the Best Fit for VLSI Partitioning - Physical Design,” 2010 International Conference on Advances in Recent Technologies in Communication and Computing, pp. 330-332, 2010. Crossref, https://doi.org/10.1109/ARTCom.2010.93.
[12] R. Bazylevych, and L. Bazylevych, “The Methodology and Algorithms for Solving the Very Large-Scale Physical Design Automation Problems: Partitioning, Packaging, Placement and Routing,” 2013 2nd Mediterranean Conference on Embedded Computing, pp. 1-2, 2013. Crossref, https://doi.org/10.1109/MECO.2013.6601386
[13] K. Khan et al., “A New Efficient Layer Assignment Algorithm for Partitioning in 3D VLSI Physical Design,” 2013 1st International Conference on Emerging Trends and Applications in Computer Science, pp. 203-207, 2013. Crossref, https://doi.org/10.1109/ICETACS.2013.6691423
[14] J. Hinay shelly, and B. Craige Shreen, “D flip flops for Linear Response Shift Register in CMOS technology,” SSRG International Journal of VLSI & Signal Processing, vol. 4, no. 3, pp. 16-20, 2017. Crossref, https://doi.org/10.14445/23942584/IJVSP-V4I5P104
[15] B. Sinha et al., “Heuristics in Physical Design Partitioning: A Review,” 2015 International Conference on Innovations in Information, Embedded and Communication Systems, pp. 1-5, 2015. Crossref, https://doi.org/10.1109/ICIIECS.2015.7192900
[16] Sadiq M. Sait, Feras Chikh Oughali, and Mohammed Al-Asli, “Style Layer Assignment and Partitioning for 3d Integrated Circuits Mistreatment Tabu Search and Simulated Annealing,” Journal of Applied Analysis and Technology, vol. 14, no. 1, pp. 67-76, 2016.
[17] P. Rajeswari, and S. T. Chandra, “A Survey on an Optimal Solution for VLSI Circuit Partitioning in physical design using DPSO & DFFA Algorithms,” 2017 International Conference on Intelligent Sustainable Systems, pp. 868-872, 2017. Crossref, https://doi.org/10.1109/ISS1.2017.8389301
[18] Sreelekshmi .S, and Pooja S. Mohan, “Area Efficient Architecture for TCAM using Hybrid Partitioned SRAM,” SSRG International Journal of Electronics and Communication Engineering, vol. 2, no. 7, pp. 26-29, 2015. Crossref, https://doi.org/10.14445/23488549/IJECE-V2I7P109
[19] Robin Andre, Sebastian Schlag, and Christian Schulz, “Memetic Multilevel Hypergraph Partitioning,” Proceedings of the Genetic and Evolutionary Computation Conference, pp. 347-354, 2018. Crossref, https://doi.org/10.1145/3205455.3205475
[20] Sumitha Manoj, and R. Surendiran, "Investigation of Duty Cycle Distortion in Clock Channels with Infinisim Clockedge Technology," International Journal of Engineering Trends and Technology, vol. 70, no. 4, pp.457-464, 2022. Crossref, https://doi.org/10.14445/22315381/IJETT-V70I4P238. 
[21] X. Lei et al., “A New Multilevel Circuit Partitioning Algorithm Based on the Improved Kl Algorithm,” 2019 IEEE 5th Intl Conference on Big Data Security on Cloud, IEEE International Conference on High Performance and Smart Computing, and IEEE International Conference on Intelligent Data and Security, pp. 178-182, 2019. Crossref, https://doi.org/10.1109/BigDataSecurity-HPSC-IDS.2019.00041
[22] Shikha Arora et al., “Hybrid Algorithm PSO and SA in Achieving Partitioning Optimization for VLSI Applications,” International Journal of P2P Network Trends and Technology, vol. 2, no. 1, pp. 1-4, 2012.
[23] Rajeswari, P, and S Theodore Chandra, “A Survey on an Optimal Solution for VLSI Circuit Partitioning in Physical Design using DPSO & DFFA algorithms,” 2017 International Conference on Intelligent Sustainable Systems, pp. 868-872, 2017. Crossref, https://doi.org/10.1109/ISS1.2017.8389301
[24] Rajeswari. P, Theodore S. Chandra, and Amith Kiran Kumar, “Synthesis of VLSI Structural Cell Partitioning Using Genetic Algorithm,” ICT Systems and Sustainability, Springer, pp. 279-287, 2021. Crossref, https://doi.org/10.1007/978-981-15-8289- 9_26
[25] S. Roy, and S. Banerjee, “An Efficient Genetic Algorithm Based Multi-Objective Optimization Technique for VLSI Circuit Partitioning with Reduced Power Consumption,” 2021 5th International Conference on Electrical, Electronics, Communication, Computer Technologies and Optimization Techniques, pp. 741-745, 2021. Crossref, https://doi.org/10.1109/ICEECCOT52851.2021.9708020
[26] Peng, Shaojun et al., “A Discrete PSO for Partitioning in VLSI Circuit,” 2009 International Conference on Computational Intelligence and Software Engineering, pp. 1-4, 2009. Crossref, https://doi.org/10.1109/CISE.2009.5364339
[27] Pradip Kumar Sharma, and M. Kaur, “A Discrete FireFly Algorithm for VLSI Circuit Partitioning,” 2014 International Conference on Electronics and Communication Systems, pp. 1-4, 2014. Crossref, https://doi.org/10.1109/ECS.2014.6892764
[28] L. Lyu, and T. Yoshimura, “A Force Directed Partitioning Algorithm for 3D Floorplanning,” 2017 IEEE 12th International Conference on ASIC, pp. 718-721, 2017. Crossref, https://doi.org/10.1109/ASICON.2017.8252576
[29] Rajeswari P et al., “Associate Degree Investigation on Basic Ideas of Particle Swarm Optimisation Algorithmic Program for VLSI Design,” International Journal of Engineering and Techniques, 2018.
[30] Ghasem Pasandi, and Massoud Pedram,“A Graph Partitioning Algorithmic Program with Application in Synthesizing Single Flux Quantum Logic Circuits,” arXiv.org,Xiv:1810.00134, 2018. Crossref, https://doi.org/10.48550/arXiv.1810.00134