A New Multilevel Inverter Topology for Symmetrical and Asymmetrical Configuration

International Journal of Electrical and Electronics Engineering

© 2023 by SSRG - IJEEE Journal

Volume 10 Issue 8

Year of Publication : 2023

Authors : K. S. S. Prasad Raju, K. Vaisakh

10.14445/23488379/IJEEE-V10I8P103

How to Cite?

K. S. S. Prasad Raju, K. Vaisakh, "A New Multilevel Inverter Topology for Symmetrical and Asymmetrical Configuration," SSRG International Journal of Electrical and Electronics Engineering, vol. 10,  no. 8, pp. 23-36, 2023. Crossref, https://doi.org/10.14445/23488379/IJEEE-V10I8P103

Abstract:

Inverters with innovative modular symmetrical and asymmetrical topologies were introduced in this study. Either an isolated DC source, an additive or subtractive combination with other DC sources is used to produce the multilevel output. This study presents a novel approach (an alternate quinary sequence) for selecting magnitude input dc voltage sources. Phase Opposition Disposition (POD) pulse width modulation approach is used for pulse generation to the suggested topology. Regarding cost function, switch count and DC source count, the suggested topology performs better than a few current topologies. Switching states were derived to develop 5-Level, 9-Level, and 49-Level suggested topology. The proposed topology's validity is verified by simulation, and the prototype was developed for nine-level output voltage.

Keywords:

Modeling of switching pulses, POD technique, Symmetrical and asymmetrical multilevel inverter, Selection of DC sources.

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