Design and Analysis of Low Power Hybrid Logic Adder for Signal Processing Applications

International Journal of Electrical and Electronics Engineering

© 2023 by SSRG - IJEEE Journal

Volume 10 Issue 10

Year of Publication : 2023

Authors : Amgoth Laxman, N. Siva Sankara Reddy, B. Rajendra Naik

10.14445/23488379/IJEEE-V10I10P118

How to Cite?

Amgoth Laxman, N. Siva Sankara Reddy, B. Rajendra Naik, "Design and Analysis of Low Power Hybrid Logic Adder for Signal Processing Applications," SSRG International Journal of Electrical and Electronics Engineering, vol. 10,  no. 10, pp. 197-206, 2023. Crossref, https://doi.org/10.14445/23488379/IJEEE-V10I10P118

Abstract:

The primary objectives of VLSI design have been to enhance efficiency, reduce power consumption and delay, and minimize area. The current investigation outlines our suggested approach for analyzing a 1-bit hybrid adder compared to different adders concerning power consumption, transistor count, and delay. Recent research introduces a novel method for designing a 1-bit adder utilizing hybrid logic. An evaluation of the circuit’s efficiency has been carried out using the Mentor Graphics tool set. A statistical comparison has been conducted to examine the parameters of the course concerning the parameters of already-present adder circuits. The adder under consideration has been extended to support a width of four bits, thereby enabling an assessment of its potential for scalability. Simulation findings suggest that the proposed architecture demonstrates noteworthy performance enhancements regarding power usage and delay, leading to a comparatively low power delay product. The results obtained from the simulation illustrate that the suggested hybrid adder circuit offers a viable option for the data path structure in contemporary applications that operate at high speeds.

Keywords:

Adder, Delay, Hybrid logic, Power consumption, Transistor count.

References:

[1] Fabio Frustaci et al., “Designing High-Speed Adders in Power-Constrained Environments,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 56, no. 2, pp. 172-176, 2009.
[CrossRef] [Google Scholar] [Publisher Link]
[2] Ajit Pal, Low Power VLSI Circuits and Systems, Springer India, New Delhi, 2015.
[CrossRef] [Google Scholar] [Publisher Link]
[3] Ning Zhu, Wang Ling Goh, and Kiat Seng Yeo, “An Enhanced Low-Power High-Speed Adder for Error Tolerant Application,” Proceedings of the 2009 12th International Symposium on Integrated Circuits, Singapore, pp. 69-72, 2009.
[Google Scholar] [Publisher Link]
[4] Alberto A. Del Barrio et al., “Applying Speculation Techniques to Implement Functional Units,” 2008 IEEE International Conference on Computer Design, Lake Tahoe, CA, USA, pp. 74-80, 2008.
[CrossRef] [Google Scholar] [Publisher Link]
[5] B. Krishna Naga Deepthi, and M.V. Subramanyam, “Analysis and Optimization of Power Consumption and Area of Domino Full Adder,” SSRG International Journal of VLSI & Signal Processing, vol. 2, no. 2, pp. 14-19, 2015.
[CrossRef] [Publisher Link]
[6] Kai Du, Peter Varman, and Kartik Mohanram, “High Performance Reliable Variable Latency Carry Select Addition,” 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), Dresden, Germany, pp. 1257-1262, 2012.
[CrossRef] [Google Scholar] [Publisher Link]
[7] Darjn Esposito et al., “Variable Latency Speculative Han-Carlson Adder,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 62, no. 5, pp. 1353-1361, 2015.
[CrossRef] [Google Scholar] [Publisher Link]
[8] Omid Akbari et al., “RAP-CLA: A Reconfigurable Approximate Carry Lookahead Adder,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 65, no. 8, pp. 1089-1093, 2018.
[CrossRef] [Google Scholar] [Publisher Link]
[9] Basant Kumar Mohanty, “Efficient Fixed-Width Adder-Tree Design,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 66, no. 2, pp. 292-296, 2019.
[CrossRef] [Google Scholar] [Publisher Link]
[10] Sohan Purohit, and Martin Margala, “Investigating the Impact of Logic and Circuit Implementation for Full Adder Performance,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 20, no. 7, pp. 1327-1331, 2012.
[CrossRef] [Google Scholar] [Publisher Link]
[11] R. Zimmermann, and W. Fichtner, “Low-Power Logic Styles: CMOS Versus Pass-Transistor Logic,” IEEE Journal of Solid-State Circuits, vol. 32, no. 7, pp. 1079-1090, 1997.
[CrossRef] [Google Scholar] [Publisher Link]
[12] Yingtao Jiang et al., “A Novel Multiplexer-Based Low-Power Full Adder,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 51, no. 7, pp. 345-348, 2004.
[CrossRef] [Google Scholar] [Publisher Link]
[13] Neil H.E. Weste, and David Money Harris, CMOS VLSI Design: A Circuits and Systems Perspective, 4th ed., Addison-Wesley, Boston, MA, USA, 2010.
[Google Scholar] [Publisher Link]
[14] Amrutavarshini S.H., and S. Pramod Kumar, “High-Speed and Energy-Efficient Carry Skip Adder Functioning under a Extensive Range of Supply Voltage Levels,” SSRG International Journal of VLSI & Signal Processing, vol. 4, no. 2, pp. 1-5, 2017.
[CrossRef] [Google Scholar] [Publisher Link]
[15] A.M. Shams, T.K. Darwish, and M.A. Bayoumi, “Performance Analysis of Low-Power 1-Bit CMOS Full Adder Cells,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 10, no. 1, pp. 20-29, 2002.
[CrossRef] [Google Scholar] [Publisher Link]
[16] Chip-Hong Chang, Jiangmin Gu, and Mingyan Zhang, “A Review of 0.18-μm Full Adder Performances for Tree Structured Arithmetic Circuits,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 13, no. 6, pp. 686-695, 2005.
[CrossRef] [Google Scholar] [Publisher Link]
[17] M. Alioto, G. Di Cataldo, and G. Palumbo, “Mixed Full Adder Topologies for High-Performance Low-Power Arithmetic Circuits,” Microelectronics Journal, vol. 38, no. 1, pp. 130-139, 2007.
[CrossRef] [Google Scholar] [Publisher Link]
[18] Seyed Erfan Fatemieh, Samira Shirinabadi Farahani, and Mohammad Reza Reshadinezhad, “LAHAF: Low-Power, Area-Efficient, and High-Performance Approximate Full Adder Based on Static CMOS,” Sustainable Computing: Informatics and Systems, vol. 30, 2021.
[CrossRef] [Google Scholar] [Publisher Link]
[19] Mehedi Hasan et al., “Design of a Scalable Low-Power 1-Bit Hybrid Full Adder for Fast Computation,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 67, no. 8, pp. 1464-1468, 2020.
[CrossRef] [Google Scholar] [Publisher Link]
[20] Jyoti Kandpal et al., “High-Speed Hybrid-Logic Full Adder Using High-Performance 10-T XOR–XNOR Cell,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 28, no. 6, pp. 1413-1422, 2020.
[CrossRef] [Google Scholar] [Publisher Link]
[21] Mohammad Mirzaei, and Siamak Mohammadi, “Process Variation-Aware Approximate Full Adders for Imprecision-Tolerant Applications,” Computers & Electrical Engineering, vol. 87, 2020.
[CrossRef] [Google Scholar] [Publisher Link]
[22] Shivani Bathla, Rahul M. Rao, and Nitin Chandrachoodan, “A Simulation-Based Metric to Guide Glitch Power Reduction in Digital Circuits,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 27, no. 2, pp. 376-386, 2019.
[CrossRef] [Google Scholar] [Publisher Link]
[23] Chiou-Kou Tung et al., “A Low-Power High-Speed Hybrid CMOS Full Adder for Embedded System,” 2007 IEEE Design and Diagnostics of Electronic Circuits and Systems, Krakow, Poland, pp. 1-4, 2007.
[CrossRef] [Google Scholar] [Publisher Link]
[24] Mariano Aguirre-Hernandez, and Monico Linares-Aranda, “CMOS Full-Adders for Energy-Efficient Arithmetic Applications,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 19, no. 4, pp. 718-721, 2011.
[CrossRef] [Google Scholar] [Publisher Link]
[25] Sumeer Goel, Ashok Kumar, and Magdy A. Bayoumi, “Design of Robust, Energy Efficient Full Adders for Deep-Submicrometer Design Using Hybrid-CMOS Logic Style,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 14, no. 12, pp. 1309-1321, 2006.
[CrossRef] [Google Scholar] [Publisher Link]
[26] Ilham Hassoune et al., “ULPFA: A New Efficient Design of a Power-Aware Full Adder,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 57, no. 8, pp. 2066-2074, 2010.
[CrossRef] [Google Scholar] [Publisher Link]
[27] Reza Faghih Mirzaee et al., “A New Robust and Hybrid High-Performance Full Adder Cell,” Journal of Circuits, Systems and Computers, vol. 20, no. 4, pp. 641-655, 2011.
[CrossRef] [Google Scholar] [Publisher Link]
[28] M.C. Parameshwara, and H.C. Srinivasaiah, “Low-Power Hybrid 1-Bit Full Adder Circuit for Energy Efficient Arithmetic Applications,” Journal of Circuits, Systems and Computers, vol. 26, no. 1, pp. 1-15, 2017.
[CrossRef] [Google Scholar] [Publisher Link]
[29] Pankaj Kumar, and Rajender Kumar Sharma, “An Energy Efficient Logic Approch to Implement CMOS Full Adder,” Journal of Circuits, Systems and Computers, vol. 26, no. 5, pp. 1-20, 2017.
[CrossRef] [Google Scholar] [Publisher Link]
[30] Mohan Shoba, and Rangaswamy Nakkeeran, “GDI Based Full Adders for Energy Efficient Arithmetic Applications,” Engineering Science and Technology, an International Journal, vol. 19, no. 1, pp. 485-496, 2016.
[CrossRef] [Google Scholar] [Publisher Link]