VLSI Architecture of Efficient Hybrid Multiplier Using Hybrid Adder
| International Journal of Electrical and Electronics Engineering |
| © 2023 by SSRG - IJEEE Journal |
| Volume 10 Issue 11 |
| Year of Publication : 2023 |
| Authors : Bala Sindhuri Kandula, J.S.S.D. Manikanta, S. Koteswari, Sarala Patchala |
10.14445/23488379/IJEEE-V10I11P104
How to Cite?
Bala Sindhuri Kandula, J.S.S.D. Manikanta, S. Koteswari, Sarala Patchala, "VLSI Architecture of Efficient Hybrid Multiplier Using Hybrid Adder," SSRG International Journal of Electrical and Electronics Engineering, vol. 10, no. 11, pp. 39-45, 2023. Crossref, https://doi.org/10.14445/23488379/IJEEE-V10I11P104
Abstract:
With the proliferation of digital signal processing systems and embedded systems in the VLSI era, multipliers have emerged as pivotal components. Their performance greatly influences computational speed, system area, and power consumption, impacting the overall system cost. Multipliers predominantly involve logical operations in computing additions for partial product generation. To enhance the efficiency of these multipliers, it is essential to minimize switching activity and reduce the architectural area using combinational optimization techniques. This research paper presents the development of hybrid multiplier architecture by employing hybrid adders and adopting optimizing strategies. The proposed hybrid multiplier architecture has been synthesized and simulated using Xilinx Vivado 2017.2, with subsequent hardware implementation conducted on the Zedboard. Experimental findings reveal a notable speed improvement when comparing the proposed hybrid multiplier to alternative multiplier designs.
Keywords:
Hardware implementation, Optimization, High-speed architecture, VLSI multiplier, Hybrid multiplier.
References:
[1] H.J. Oh, and Y.H. Lee, “Design of Discrete Coefficient FIR and IIR Digital Filters with Prefilter-Equalizer Structure Using Linear Programming,” IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 47, no. 6, pp. 562-565, 2000.
[CrossRef] [Google Scholar] [Publisher Link]
[2] Zhijun Huang, and M.D. Ercegovac, “High-Performance Low-Power Left-to-Right Array Multiplier Design,” IEEE Transactions on Computers, vol. 54, no. 3, pp. 272-283, 2005.
[CrossRef] [Google Scholar] [Publisher Link]
[3] Angshuman Khan, Ali Newaz Bahar, and Rajeev Arya, “Efficient Design of Vedic Square Calculator Using Quantum Dot Cellular Automata (QCA),” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 69, no. 3, pp. 1587-1591, 2022.
[CrossRef] [Google Scholar] [Publisher Link]
[4] Sridevi Sathya Priya S. et al., “Implementation of Multiplier Using Vedic Mathematics,” Materials Today: Proceedings, vol. 65, no. 9, pp. 3921-3926, 2022.
[CrossRef] [Google Scholar] [Publisher Link]
[5] Avinash Kumar Singh, and Ashutosh Nandi, “Design of Radix 2 Butterfly Structure Using Vedic Multiplier and CLA on Xilinx,” 2017 Conference on Emerging Devices and Smart Systems (ICEDSS), pp. 120-123, 2017.
[CrossRef] [Google Scholar] [Publisher Link]
[6] Rashi Khubnani, Tarunika Sharma, and Chitirala Subramanyam, “Applications of Vedic Multiplier - A Review,” Journal of Physics: Conference Series, vol. 2225, 2022.
[CrossRef] [Google Scholar] [Publisher Link]
[7] Thangam C., “Implementation of Barrel Shifter in Vedic Multiplier,” 2022 International Conference on Sustainable Computing and Data Communication Systems (ICSCDS), India, pp. 774-777, 2022.
[CrossRef] [Google Scholar] [Publisher Link]
[8] Aruru Sai Kumar et al., “Design of High Speed 8-Bit Vedic Multiplier Using Brent Kung Adders,” 2022 13th International Conference on Computing Communication and Networking Technologies (ICCCNT), India, pp. 1-5, 2022.
[CrossRef] [Google Scholar] [Publisher Link]
[9] Aditi Awasthy, “VLSI Implementation of Multiplier and Adder Circuits with Vedic Algorithm Computation,” 2022 First International Conference on Electrical, Electronics, Information and Communication Technologies (ICEEICT), India, pp. 1-4, 2022.
[CrossRef] [Google Scholar] [Publisher Link]
[10] Anbumani V. et al., “Speed and Power Efficient Vedic Multiplier Using Adders with MUX,” 2021 Innovations in Power and Advanced Computing Technologies (i-PACT), Malaysia, pp. 1-5, 2021.
[CrossRef] [Google Scholar] [Publisher Link]
[11] Arti Kumari et al., “Design and Implementation of 12-Bit Vedic Multiplier Using Optimized Decoder-Based Adder,” 2021 International Conference on Simulation, Automation and Smart Manufacturing (SASM), India, pp. 1-5, 2021.
[CrossRef] [Google Scholar] [Publisher Link]
[12] Yogeshwaran K. et al., “Design and Simulation of 16x16 Vedic Multiplier Using Kogge-Stone Adder,” 2023 7th International Conference on Computing Methodologies and Communication (ICCMC), India, pp. 452-457, 2023.
[CrossRef] [Google Scholar] [Publisher Link]
[13] Ramin Barati, “High Speed Low Power Multipliers Based on Reversible Logic Methods,” e-Prime - Advances in Electrical Engineering, Electronics and Energy, vol. 2, pp. 1-7, 2022.
[CrossRef] [Google Scholar] [Publisher Link]
[14] Abhijeet Patil, “Create a 32-bit Vedic Multiplier and Compare it against other Multipliers Using a Carry Look-Ahead Adder,” 2023 4th International Conference for Emerging Technology (INCET), India, pp. 1-4, 2023.
[CrossRef] [Google Scholar] [Publisher Link]
[15] A. Haripriya, S. Nagaraj, and Samanth C., “Design and Analysis of 16-Bit Vedic Multiplier Using RCA and CSLA,” 2023 International Conference on Signal Processing, Computation, Electronics, Power and Telecommunication (IConSCEPT), India, pp. 1-5, 2023.
[CrossRef] [Google Scholar] [Publisher Link]
[16] V. Thamizharasan, and N. Kasthuri, “High-Speed Hybrid Multiplier Design Using a Hybrid Adder with FPGA Implementation,” IETE Journal of Research, vol. 69, no. 5, pp. 2301-2309, 2021.
[CrossRef] [Google Scholar] [Publisher Link]
[17] G. Challa Ram et al., “Area Efficient Modified Vedic Multiplier,” 2016 International Conference on Circuit, Power and Computing Technologies (ICCPCT), India, pp. 1-5, 2016.
[CrossRef] [Google Scholar] [Publisher Link]
[18] Avinash Kumar Singh, and Ashutosh Nandi, “Design of Radix 2 Butterfly Structure Using Vedic Multiplier and CLA on Xilinx,” 2017 Conference on Emerging Devices and Smart Systems (ICEDSS), India, pp. 120-123, 2017.
[CrossRef] [Google Scholar] [Publisher Link]
[19] Lakshmanan, A. Meaamar, and Masuri Othman, “High-Speed Hybrid Parallel-Prefix Carry-Select Adder Using Ling’s Algorithm,” 2006 IEEE International Conference on Semiconductor Electronics, Malaysia, pp. 598-602, 2006.
[CrossRef] [Google Scholar] [Publisher Link]
[20] Nidhi Gaur et al., “16 Bit Power Efficient Carry Select Adder,” 2019 6th International Conference on Signal Processing and Integrated Networks (SPIN), India, pp. 558-561, 2019.
[CrossRef] [Google Scholar] [Publisher Link]
[21] Sreenivaas Muthyala Sudhakar, Kumar P. Chidambaram, and Earl E. Swartzlander, “Hybrid Han-Carlson Adder,” 2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS), USA, pp. 818-821, 2012.
[CrossRef] [Google Scholar] [Publisher Link]
[22] Neha Varshney, and Greeshma Arya, “Design and Execution of Enhanced Carry Increment Adder Using Han-Carlson and Kogge-Stone Adder Technique,” Third International Conference on Electronics Communication and Aerospace Technology (ICECA 2019), India, pp. 1163-1170, 2019.
[CrossRef] [Google Scholar] [Publisher Link]
[23] R. Suganya, and D. Meganathan, “High Performance VLSI Adders,” 2015 3rd International Conference on Signal Processing, Communication and Networking (ICSCN), India, pp. 1-7, 2015.
[CrossRef] [Google Scholar] [Publisher Link]
[24] V. Thamizharasan, and N. Kasthuri, “Design of Proficient Two Operand Adder Using Hybrid Carry Select Adder with FPGA Implementation,” IETE Journal of Research, pp. 1-14, 2022.
[CrossRef] [Google Scholar] [Publisher Link]