Distinct ρ-Based DGMOSFET Analysis for Ternary Content Addressable Memory at Sub-nm VLSI Technology

International Journal of Electrical and Electronics Engineering

© 2023 by SSRG - IJEEE Journal

Volume 10 Issue 12

Year of Publication : 2023

Authors : Hameed Pasha Mohammad, Meghana Kulkarni, Sandeep Kyatanavar, H.C. Hadimani

10.14445/23488379/IJEEE-V10I12P105

How to Cite?

Hameed Pasha Mohammad, Meghana Kulkarni, Sandeep Kyatanavar, H.C. Hadimani, "Distinct ρ-Based DGMOSFET Analysis for Ternary Content Addressable Memory at Sub-nm VLSI Technology," SSRG International Journal of Electrical and Electronics Engineering, vol. 10,  no. 12, pp. 37-53, 2023. Crossref, https://doi.org/10.14445/23488379/IJEEE-V10I12P105

Abstract:

A leading-edge sub-nm digital logic technology related to Ternary Content Addressable Memory (TCAM) based binary-memory cell by scaling the CMOS technology has increased the implications of leakage-current and power-analysis for memory design. Conventional TCAM designs have a dynamic CMOS circuit architecture to improve matching speed; however, these implementations have to overcome design limitations, such as process variations of Short-Channel Effects (SCEs). To minimize the SCEs, in this work, a distinct ρ-based DGMOSFET TCAM circuit, binary-memory cell for low-power, available speed-and-area TCAM, using a particular ρ-based binary-memory switch for non-volatile memory data storage is designed. Simulation-based on a distinct ρ-based binary-memory mathematical model analyzed by sub-nm-MOS model parameters. The proposed design analysis and simulation results show better value improvement in delay and energy/bit/search for 64x64-bit TCAM comparatively.

Keywords:

TCAM, SCE, DGMOSFET, Sub-nm, Low power.

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