Conceptualization and Design of 8-Bit SRAM Using Quantum Dot Cellular Automata
| International Journal of Electrical and Electronics Engineering |
| © 2024 by SSRG - IJEEE Journal |
| Volume 11 Issue 1 |
| Year of Publication : 2024 |
| Authors : Smita C. Chetti, M.B. Veena |
10.14445/23488379/IJEEE-V11I1P103
How to Cite?
Smita C. Chetti, M.B. Veena, "Conceptualization and Design of 8-Bit SRAM Using Quantum Dot Cellular Automata," SSRG International Journal of Electrical and Electronics Engineering, vol. 11, no. 1, pp. 14-27, 2024. Crossref, https://doi.org/10.14445/23488379/IJEEE-V11I1P103
Abstract:
In the current landscape, nanotechnology stands as the foremost area of research, striving to shrink device sizes. Among the array of techniques within nanotechnology, Quantum-dot Cellular Automata (QCA) is heralded for its remarkable efficiency: boosting operating frequencies, minimal power consumption, and superior density. When it comes to designing circuits using Quantum dot Cellular Automata (QCA), the traditional method involves arranging these QCA cells in specific ways to achieve desired functions. Creating higher-level circuits is complex, and troubleshooting is even more challenging. However, this technology has the potential to execute all designs possible with CMOS technology. As per the existing works, the latch and flip-flop design is mainly considered only for storing data. An alternative to the traditional design is the hierarchical approach, which proposes an 8-bit memory element design in this paper. This paper proposes the inclusion of read and write signals in the memory register designed using QCA so that read/write signals can enable efficient access to the specific memory units. The proposed design occupies less area, QCA cells, and latency as well, thus leading to less circuit cost compared to existing works. Another precedence of this paper is the repeatability and regularity of the design, which aids in expanding the design size and can be applied to increase memory capacity as needed by making appropriate modifications to the designs. The results are simulated using the QCA Designer 2.0.3 tool for verification of obtained results. These designs can further be combined with other designs for application development.
Keywords:
Clock zones, D Flip-Flop (DFF), Driver cells, Fixed cell, Normal cell, Polarized cells, SRAM.
References:
[1] C.S. Lent et al., “Quantum-Dot Cellular Automata,” Electron Transport in Quantum Dots, pp. 397-431, 2003.
[CrossRef] [Google Scholar] [Publisher Link]
[2] Weiqiang Liu et al., “A First Step toward Cost Functions for Quantum-Dot Cellular Automata Designs,” IEEE Transactions on Nanotechnology, vol. 13, no. 3, pp. 476-487, 2014.
[CrossRef] [Google Scholar] [Publisher Link]
[3] Sanjukta Bhanja, and Sudeep Sarkar, “Probabilistic Modeling of QCA Circuits Using Bayesian Networks,” IEEE Transactions on Nanotechnology, vol. 5, no. 6, pp. 657-670, 2006.
[CrossRef] [Google Scholar] [Publisher Link]
[4] S.C. Henderson et al., “Incorporating Standard CMOS Design Process Methodologies into the QCA Logic Design Process,” IEEE Transactions on Nanotechnology, vol. 3, no. 1, pp. 2-9, 2004.
[CrossRef] [Google Scholar] [Publisher Link]
[5] Joao G. Nizer Rahmeier et al., “A Novel Crossing Device for In-Plane Nanomagnetic Logic Circuits,” 2018 IEEE 18th International Conference on Nanotechnology (IEEE-NANO), Cork, Ireland, pp. 1-4, 2018.
[CrossRef] [Google Scholar] [Publisher Link]
[6] P. Douglas Tougaw, and Craig S. Lent, “Logical Devices Implemented Using Quantum Cellular Automata,” Journal of Applied Physics, vol. 75, pp. 1818-1825, 1994.
[CrossRef] [Google Scholar] [Publisher Link]
[7] Dharmendra Kumar, and Debasis Mitra, “A Systematic Approach towards Fault-Tolerant Design of QCA Circuits,” Analog Integrated Circuits and Signal Processing, vol. 98, pp. 501-515, 2019.
[CrossRef] [Google Scholar] [Publisher Link]
[8] V.M. Nanditha et al., “Design and Analysis of Digital Circuits Using Quantum Cellular Automata and Verilog,” 2020 7th International Conference on Computing for Sustainable Global Development (INDIACom), New Delhi, India, pp. 205-210, 2020.
[CrossRef] [Google Scholar] [Publisher Link]
[9] C.S. Lent, and B. Isaksen, “Clocked Molecular Quantum-Dot Cellular Automata,” IEEE Transactions on Electron Devices, vol. 50, no. 9, pp. 1890-1896, 2003.
[CrossRef] [Google Scholar] [Publisher Link]
[10] Aishwarya Kaity, Sangeeta Singh, and Kabirul Hossain, “Quantum Dot Cellular Automata‐Based Encoder and Priority Encoder Circuits: Low Latency and Area Efficient Design,” International Journal of Numerical Modelling: Electronic Networks, Devices and Fields, vol. 34, no. 3, 2021.
[CrossRef] [Google Scholar] [Publisher Link]
[11] Debashis De, and Jadav Chandra Das, “Design of Novel Carry Save Adder Using Quantum Dot-Cellular Automata,” Journal of Computational Science, vol. 22, pp. 54-68, 2017.
[CrossRef] [Google Scholar] [Publisher Link]
[12] Moein Kianpour, and Reza Sabbaghi-Nadooshan, “A Novel Modular Decoder Implementation in Quantum-Dot Cellular Automata (QCA),” 2011 International Conference on Nanoscience, Technology and Societal Implications, Bhubaneswar, India, pp. 1-5, 2011.
[CrossRef] [Google Scholar] [Publisher Link]
[13] Jacob Retallick, and Konrad Walus, “Low-Energy Eigenspectrum Decomposition (LEED) of Quantum-Dot Cellular Automata Networks,” IEEE Transactions on Nanotechnology, vol. 20, pp. 104-112, 2021.
[CrossRef] [Google Scholar] [Publisher Link]
[14] Bibhash Sen et al., “Multilayer Design of QCA Multiplexer,” 2013 Annual IEEE India Conference (INDICON), Mumbai, India, pp. 1-6, 2013.
[CrossRef] [Google Scholar] [Publisher Link]
[15] Sonia Afrooz, and Nima Jafari Navimipour, “An Effective Nano Design of Demultiplexer Architecture Based on Coplanar Quantum-Dot Cellular Automata,” IET Circuits Devices Systems, vol. 15, no. 2, pp. 168-174, 2021.
[CrossRef] [Google Scholar] [Publisher Link]
[16] Jun-Cheol Jeon, ‘Designing Nanotechnology QCA–Multiplexer Using Majority Function-Based NAND for Quantum Computing,” The Journal of Supercomputing, vol. 77, pp. 1562-1578, 2021.
[CrossRef] [Google Scholar] [Publisher Link]
[17] Firdous Ahmad, “An Optimal Design of QCA Based 2n:1/1:2n Multiplexer/Demultiplexer and Its Efficient Digital Logic Realization,” Microprocessors and Microsystems, vol. 56, pp. 64-75, 2018.
[CrossRef] [Google Scholar] [Publisher Link]
[18] Moein Kianpour, Reza Sabbaghi-Nadooshan, and Keivan Navi, “A Novel Design of 8-Bit Adder/Subtractor by Quantum-Dot Cellular Automata,” Journal of Computer and System Sciences, vol. 80, no. 7, pp. 1404-1414, 2014.
[CrossRef] [Google Scholar] [Publisher Link]
[19] Shaahin Angizi et al., “Novel Robust Single Layer Wire Crossing Approach for Exclusive OR Sum of Products Logic Design with Quantum-Dot Cellular Automata,” Journal of Low Power Electronics, vol. 10, no. 2, pp. 259-271, 2014.
[CrossRef] [Google Scholar] [Publisher Link]
[20] S. Hashemi, and K. Navi, “A Novel Robust QCA Full-Adder,” Procedia Materials Science, vol. 11, pp. 376-380, 2015.
[CrossRef] [Google Scholar] [Publisher Link]
[21] Dariush Abedi, Ghassem Jaberipur, and Milad Sangsefidi, “Coplanar Full Adder in Quantum-Dot Cellular Automata via Clock-Zone-Based Crossover,” IEEE Transactions on Nanotechnology, vol. 14, no. 3, pp. 497-504, 2015.
[CrossRef] [Google Scholar] [Publisher Link]
[22] Trailokya Nath Sasamal, Ashutosh Kumar Singh, and Anand Mohan, “An Efficient Design of Quantum-Dot Cellular Automata Based 5- Input Majority Gate with Power Analysis,” Microprocessors and Microsystems, vol. 59, pp. 103-117, 2018.
[CrossRef] [Google Scholar] [Publisher Link]
[23] Amjad Almatrood, Aby K. George, and Harpreet Singh, “Low-Power Multiplexer Structures Targeting Efficient QCA Nanotechnology Circuit Designs,” Electronics, vol. 10, no. 16, pp. 1-11, 2021.
[CrossRef] [Google Scholar] [Publisher Link]
[24] Hamid Rashidi, and Abdalhossein Rezai, “Design of Novel Efficient Multiplexer Architecture for Quantum-Dot Cellular Automata,” Journal of Nano-and Electronic Physics, vol. 9, no. 1, pp. 1-7, 2017.
[Google Scholar]
[25] Shahram Babaie, Ali Sadoghifar, and Ali Newaz Bahar, “Design of an Efficient Multilayer Arithmetic Logic Unit in Quantum-Dot Cellular Automata (QCA),” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 66, no. 6, pp. 963-967, 2019.
[CrossRef] [Google Scholar] [Publisher Link]
[26] Nuriddin Safoev, and Jun-Cheol Jeon, “Low Area Complexity Demultiplexer Based on Multilayer Quantum-Dot Cellular Automata,” International Journal of Control and Automation, vol. 9, no. 12, pp. 165-178, 2016.
[CrossRef] [Google Scholar] [Publisher Link]
[27] Vijay Kumar Sharma, “Optimal Design for 1:2 Demultiplexer Using QCA Nanotechnology with Energy Dissipation Analysis,” International Journal of Numerical Modelling: Electronic Networks, Devices and Fields, vol. 34, no. 6, 2021.
[CrossRef] [Google Scholar] [Publisher Link]
[28] R. Karthik, and S.R. Kassa, “Implementation of Flip Flops Using QCA Tool,” Journal of Applied and Fundamental Sciences, vol. 10, no. 6S, pp. 2332-2341, 2018.
[CrossRef] [Google Scholar] [Publisher Link]
[29] Frank Sill Torres et al., “An Energy-Aware Model for the Logic Synthesis of Quantum-Dot Cellular Automata,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 37, no. 12, pp. 3031-3041, 2018.
[CrossRef] [Google Scholar] [Publisher Link]
[30] Sara Hashemi, and Keivan Navi, “New Robust QCAD Flip Flop and Memory Structures,” Microelectronics Journal, vol. 43, no. 12, pp. 929-940, 2012.
[CrossRef] [Google Scholar] [Publisher Link]
[31] Trailokya Nath Sasamal, Ashutosh Kumar Singh, and Umesh Ghanekar, “Design and Implementation of QCA D-Flip-Flops and RAM Cell Using Majority Gates,” Journal of Circuits, Systems and Computers, vol. 28, no. 5, 2019.
[CrossRef] [Google Scholar] [Publisher Link]
[32] Reza Binaei, and Mohammad Gholami, “Design of Novel D Flip-Flops with Set and Reset Abilities in Quantum-Dot Cellular Automata Nanotechnology,” Computers & Electrical Engineering, vol. 74, pp. 259-272, 2019.
[CrossRef] [Google Scholar] [Publisher Link]
[33] Saeid Zoka, and Mohammad Gholami, “A Novel Rising Edge Triggered Resettable D Flip-Flop Using Five Input Majority Gate,” Microprocessors and Microsystems, vol. 61, pp. 327-335, 2018.
[CrossRef] [Google Scholar] [Publisher Link]
[34] Milad Bagherian Khosroshahy et al., “An Energy and Cost Efficient Majority-Based RAM Cell in Quantum-Dot Cellular Automata,” Results in Physics, vol. 7, pp. 3543-3551, 2017.
[CrossRef] [Google Scholar] [Publisher Link]
[35] Azath Mubarakali et al., “A New Efficient Design for Random Access Memory Based on Quantum Dot Cellular Automata Nanotechnology,” Nano Communication Networks, vol. 21, 2019.
[CrossRef] [Google Scholar] [Publisher Link]
[36] Trailokya Nath Sasamal, Ashutosh Kumar Singh, and Umesh Ghanekar, “Design of QCA-Based D Flip Flop and Memory Cell Using Rotated Majority Gate,” Smart Innovations in Communication and Computational Sciences, vol. 670, pp. 233-247, 2018.
[CrossRef] [Google Scholar] [Publisher Link]
[37] Moein Kianpour, and Reza Sabbaghi-Nadooshan, “A Novel Quantum-Dot Cellular Automata X-bit × 32-bit SRAM,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 24, no. 3, pp. 827-836, 2016.
[CrossRef] [Publisher Link]