Review Paper on Reversible Multiplier Circuit using Different Programmable Reversible Gate

International Journal of Electrical and Electronics Engineering

© 2015 by SSRG - IJEEE Journal

Volume 2 Issue 10

Year of Publication : 2015

Authors : Shweta Baraniya, Sujeet Mishra

10.14445/23488379/IJEEE-V2I10P104

How to Cite?

Shweta Baraniya, Sujeet Mishra, "Review Paper on Reversible Multiplier Circuit using Different Programmable Reversible Gate," SSRG International Journal of Electrical and Electronics Engineering, vol. 2,  no. 10, pp. 16-20, 2015. Crossref, https://doi.org/10.14445/23488379/IJEEE-V2I10P104

Abstract:

 Reversible logic circuits are increasingly used in power minimization having applications such as low power CMOS design, optical information processing, DNA computing, bioinformatics, quantum computing and nanotechnology. The problem of minimizing the number of garbage outputs is an important issue in reversible logic design. In this paper we have design 5×5 reversible logic gate using programmable reversible gate. We have used different types of programmable reversible gate i.e. Peres gate (PG) and HNG gate, PG and DPG gate, PG and full adder, PG and MHNG to construct the reversible fault tolerant multiplier circuit. We show that the 5×5 reversible multiplier circuit has lower hardware complexity and it is much better and optimized in terms of number of reversible gates and number of garbage outputs with compared to the existing counterparts.

Keywords:

 Peres Gate, Reversible Multiplier, Garbage Output, Quantum Cost.

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