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Design and Investigation of Hetero Vertical TFET with Source Pocket for Work Function Engineering and Analog Performance Enhancement

International Journal of Electrical and Electronics Engineering
© 2024 by SSRG - IJEEE Journal
Volume 11 Issue 5
Year of Publication : 2024
Authors : Kavindra Kumar Kavi, Ravi Kumar, Suman Dass, Chetna Sinha, Manjeet Singh Sonwani, Lavi Tyagi
10.14445/23488379/IJEEE-V11I5P128
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How to Cite?

Kavindra Kumar Kavi, Ravi Kumar, Suman Dass, Chetna Sinha, Manjeet Singh Sonwani, Lavi Tyagi, "Design and Investigation of Hetero Vertical TFET with Source Pocket for Work Function Engineering and Analog Performance Enhancement," SSRG International Journal of Electrical and Electronics Engineering, vol. 11,  no. 5, pp. 306-312, 2024. Crossref, https://doi.org/10.14445/23488379/IJEEE-V11I5P128

Abstract:

To provide a high-efficiency device, this article presents a Vertical SiGe Tunnel Field Effect Transistor (HeteroVTFET), including and not including a source pocket. For perhaps the first time, a group IV miscible alloy SiGe is exploited in the source to improve carrier tunnelling through a source (SiGe)-channel (Si) Hetero-junction. To establish an optimal HeteroVTFET design, work function engineering and hetero-junction structure tuning are used. The simulation results carried out using the TCAD Silvaco tool are used to analyze the behaviour of developed Hetero-VTFETs.  The proposed optimal structure has a higher ION/IOFF ratio (>1014), a lesser subthreshold swing (<25 mV/Dec), and a high ION current in the 10-5A/µm range.

Keywords:

Vertical Tunnel Field Effect Transistor, Source pocket, Low supply voltage, Ambipolarity, Subthreshold slope.

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