Design of Low-Power Low-Complexity High-Delay FlipFlop

International Journal of Electrical and Electronics Engineering

© 2024 by SSRG - IJEEE Journal

Volume 11 Issue 6

Year of Publication : 2024

Authors : D. Srinivas, N. Siva Sankar Reddy, B. Rajendra Naik

10.14445/23488379/IJEEE-V11I6P107

How to Cite?

D. Srinivas, N. Siva Sankar Reddy, B. Rajendra Naik, "Design of Low-Power Low-Complexity High-Delay FlipFlop," SSRG International Journal of Electrical and Electronics Engineering, vol. 11,  no. 6, pp. 58-69, 2024. Crossref, https://doi.org/10.14445/23488379/IJEEE-V11I6P107

Abstract:

 The operation of deep sub-micron digital systems is dependent on power dissipation. Power is of the utmost importance in miniature systems. This work examines the use of traditional flip-flops. This work presents a unique master-slave flip-flop that combines fast speed with low power consumption. Master and slave latches make the flip-flop structure the most successful. In this paper, the flip-flop design uses 17 transistors in total to build master and slave circuits. The level of complexity, in particular, decreases with decreasing PMOS transistor count. This design produces a fast and compact flip-flop. The circuit in question employs a single clock. The proposed research has been modelled on the 45nm technology node. The present research includes PVT analysis to validate the reliability of the flip-flop. The proposed FF has a low power usage of at least 9.22%, less leakage power of at least 17.48%, and a clock-to-output delay of at least 68.37% when compared with the existing FFs.

Keywords:

Power usage, Flip-flop, Delay, 45nm technology node, PVT analysis.

References:

[1] Daniel J. Radack, and John C. Zolper, “A Future of Integrated Electronics: Moving Off the Roadmap,” Proceedings of the IEEE, vol. 96, no. 2, pp. 198-200, 2008.
[CrossRef] [Google Scholar] [Publisher Link]
[2] Ludovic Moreau, Rémi Dekimpe, and David Bol,  “A 0.4 V 0.5 fJ/cycle TSPC Flip-Flop in 65nm LP CMOS with Retention Mode Controlled by Clock-Gating Cells,”  2019 IEEE International Symposium on Circuits and Systems (ISCAS), Sapporo, Japan, pp. 1-4, 2019.
[CrossRef] [Google Scholar] [Publisher Link]
[3] Mohammad Rahman et al., “Design Automation Tools and Libraries for Low Power Digital Design,” 2010 IEEE Dallas Circuits and Systems Workshop, Richardson, TX, USA, pp. 1-4, 2010.
[CrossRef] [Google Scholar] [Publisher Link]
[4] G. Prakash et al., “Achieveing Reduced Area by Multi-Bit Flip Flop Design,” 2013 International Conference on Computer Communication and Informatics, Coimbatore, India, pp. 1-4, 2013.
[CrossRef] [Google Scholar] [Publisher Link]
[5] G.J.Y. Lin, C.B. Hsu, and J.B. Kuo, “Critical-Path Aware Power Consumption Optimization Methodology (CAPCOM) Using MixedVTH Cells for Low-Power SOC Designs,” 2014 IEEE International Symposium on Circuits and Systems (ISCAS), Melbourne VIC, pp. 1740-1743, 2014.
[CrossRef] [Google Scholar] [Publisher Link]
[6] S. Gautam, “Analysis of Multi-Bit Flip Flop Low Power Methodology to Reduce Area and Power in Physical Synthesis and Clock Tree Synthesis in 90nm CMOS Technology,” 2014 International Conference on Advances in Computing, Communications and Informatics (ICACCI), Delhi, India, pp. 570-574, 2014.
[CrossRef] [Google Scholar] [Publisher Link]
[7] Chaochao Feng et al., “A Parameterized Timing-Aware Flip-Flop Merging Algorithm for Clock Power Reduction,” 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), Dresden, Germany, pp. 881-884, 2018.
[CrossRef] [Google Scholar] [Publisher Link]
[8] Jin-Fa Lin et al., “Low-Power 19-Transistor True Single-Phase Clocking Flip-Flop Design Based on Logic Structure Reduction Schemes,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 25, no. 11, pp. 3033-3044, 2017.
[CrossRef] [Google Scholar] [Publisher Link]
[9] Elio Consoli, Gaetano Palumbo, and Melita Pennisi, “Reconsidering High-Speed Design Criteria for Transmission-Gate-Based Master– Slave Flip-Flops,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 20, no. 2, pp. 284-295, 2012.
[CrossRef] [Google Scholar] [Publisher Link]
[10] Chen Kong The et al., “A 77% Energy-Saving 22-Transistor Single-Phase-Clocking D-Flip-Flop with Adaptive- Coupling Configuration in 40nm CMOS,” 2011 IEEE International Solid-State Circuits Conference, San Francisco, CA, USA, pp. 338-340, 2011.
[CrossRef] [Google Scholar] [Publisher Link]
[11] Natsumi Kawai et al., “A Fully Static Topologically-Compressed 21-Transistor Flip-Flop with 75% Power Saving,” IEEE Journal of Solid-State Circuits, vol. 49, no. 11, pp. 2526-2533, 2014.
[CrossRef] [Google Scholar] [Publisher Link]
[12] Jin-Fa Lin et al., “Low-Voltage and Low-Power True-Single-Phase 16-Transistor Flip-Flop Design,” Sensors, vol. 22, no. 15, pp. 1-16, 2022.
[CrossRef] [Google Scholar] [Publisher Link]
[13] Chenyu Yin et al., “SEU Hardened D Flip-Flop Design with Low Area Overhead,” Micromachines, vol. 14, no. 10, pp. 1-12, 2023.
[CrossRef] [Google Scholar] [Publisher Link]
[14] Jun-Young Park et al., “Design of a Dual Change-Sensing 24T Flip-Flop in 65 nm CMOS Technology for Ultra Low-Power System Chips,” Electronics, vol. 11, no. 6, pp. 1-10, 2022.
[CrossRef] [Google Scholar] [Publisher Link]
[15] N.A. Doshi, S.B. Dhobale, and S.R. Kakade, “LFSR Counter Implementation in CMOS VLSI,” International Journal of Computer and Information Engineering, vol. 2, no. 12, pp. 4272-4276, 2008.
[Google Scholar]
[16] A. Morgenshtein, A. Fish, and I.A. Wagner, “A Efficient Implementation of D Flip- Flop Using the GDI Technique,” 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512), Vancouver, BC, Canada, 2004.
[CrossRef] [Google Scholar] [Publisher Link] 
[17] Yassine Attaoui et al., “A New MBFF Merging Strategy for Post-Placement Power Optimization of IoT Devices,” 2021 IEEE/ACS 18th International Conference on Computer Systems and Applications (AICCSA), Tangier, Morocco, pp. 1-6, 2021.
[CrossRef] [Google Scholar] [Publisher Link]
[18] Jin-Tai Yan, Meng-Tian Chen, and Chia-Heng Yen, “Cell-Aware MBFF Utilization for Clock Power Reduction,” 2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS), Monte Carlo, Monaco, pp. 648-651, 2016.
[CrossRef] [Google Scholar] [Publisher Link]
[19] Taehee Lee, David Z. Pan, and Joon-Sung Yang, “Clock Network Optimization with Multi-Bit Flip-Flop Generation Considering Multicorner Multimode Timing Constraint,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 37, no. 1, pp. 245-256, 2018.
[CrossRef] [Google Scholar] [Publisher Link]
[20] Doron Gluzer, and Shmuel Wimer, “Probability-Driven Multi-Bit Flip-Flop Integration with Clock Gating,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 25, no. 3, pp. 1173-1177, 2017.
[CrossRef] [Google Scholar] [Publisher Link]
[21] Taehyun Kwon et al., “Virtual-Tile-Based Flip-Flop Alignment Methodology for Clock Network Power Optimization,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 28, no. 5, pp. 1256-1268, 2020.
[CrossRef] [Google Scholar] [Publisher Link]
[22] Gicheol Shin et al., “An Ultra-Low-Power Fully-Static Contention-Free Flip-Flop with Complete Redundant Clock Transition and Transistor Elimination,” IEEE Journal of Solid-State Circuits, vol. 56, no. 10, pp. 3039-3048, 2021.
[CrossRef] [Google Scholar] [Publisher Link]
[23] Yongmin Lee, Gicheol Shin, and Yoonmyung Lee, “A Fully Static True-Single-Phase-Clocked Dual-Edge-Triggered Flip-Flop for NearThreshold Voltage Operation in IoT Applications,” IEEE Access, vol. 8, pp. 40232-40245, 2020.
[CrossRef] [Google Scholar] [Publisher Link]
[24] Po-Yu Kuo et al., “A Novel Cross-Latch Shift Register Scheme for Low Power Applications,” Appliede Sciences, vol. 11, no. 1, pp. 1-11, 2021.
[CrossRef] [Google Scholar] [Publisher Link]