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Detection and Location of Hardware Trojans Using Path Delays

International Journal of Electrical and Electronics Engineering
© 2024 by SSRG - IJEEE Journal
Volume 11 Issue 6
Year of Publication : 2024
Authors : Allagadda Seetharamaraju, Arun Raaza, Omprakash Laxmanappa Mandge, M. Meena
10.14445/23488379/IJEEE-V11I6P111
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How to Cite?

Allagadda Seetharamaraju, Arun Raaza, Omprakash Laxmanappa Mandge, M. Meena, "Detection and Location of Hardware Trojans Using Path Delays," SSRG International Journal of Electrical and Electronics Engineering, vol. 11,  no. 6, pp. 101-107, 2024. Crossref, https://doi.org/10.14445/23488379/IJEEE-V11I6P111

Abstract:

The IC industry transition to a decentralized and outsourced business strategy, wherein design, inclusion, production, packaging, testing, and assembly are being performed by numerous firms around the world, must have generated issues pertaining to IP rights piracy, reverse engineering threats on IC netlists as well as layouts, cloning of ICs, and detecting deceptive chips and also Hardware Trojans (HT). Threats posed by the injection of HTs have developed as a major issue for different vendors, governmental entities, and their vendors. This paper offers a new strategy for identifying HT using path-delaydependent parametric techniques. The key advantage of this technique is that there is no requirement to compare the HT-inserted circuit to the golden reference circuit. The proposed method has been implemented in 4-bit RCA for detecting and locating the HTs.

Keywords:

IC, Hardware Trojan, RCA, Path-delay, Netlist.

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