Low Latent Fixed Width Multiplier for Error Resilient Computation

International Journal of Electrical and Electronics Engineering

© 2024 by SSRG - IJEEE Journal

Volume 11 Issue 6

Year of Publication : 2024

Authors : B.V. Srividya, S.P. Meharunnissa, Chetan Umadi, Nagarathna, Saravana Kumar

10.14445/23488379/IJEEE-V11I6P120

How to Cite?

B.V. Srividya, S.P. Meharunnissa, Chetan Umadi, Nagarathna, Saravana Kumar, "Low Latent Fixed Width Multiplier for Error Resilient Computation," SSRG International Journal of Electrical and Electronics Engineering, vol. 11,  no. 6, pp. 182-187, 2024. Crossref, https://doi.org/10.14445/23488379/IJEEE-V11I6P120

Abstract:

Many applications in signal processing have an innate ability to tolerate a certain amount of computational mistakes. The human eye’s limited capacity for perceiving images and videos makes approximation useful in computations. Hence, this concept of error resilience approach can be accommodated in the hardware to reduce the computational time in high-speed circuits. Basically, multiplication in the signal processing domain takes a longer time. Hence, approximate multipliers have been an area of interest in recent times. This paper initially deals with a detailed study of various approaches to approximate multipliers. Subsequently, a novel architecture for error-resilient multiplication is proposed wherein approximate partial products are obtained. The entire multiplication operation is divided into three modules. The architecture of these modules is designed such that it provides the approximate output. These three modules work in parallel, thereby increasing the throughput. Efficient components are used in the design to improve the performance. The proposed multiplier is designed and simulated using Cadence 45nm technology. 

Keywords:

 Error resilience, Fixed width multipliers, Signal processing, Throughput, Low latency.

References:

[1] Massimo Alioto, “Ultra-Low Power VLSI Circuit Design Demystified and Explained: A Tutorial,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 59, no. 1, pp. 3-29, 2012.
[CrossRef] [Google Scholar] [Publisher Link]
[2] Vaibhav Gupta et al., “Low-Power Digital Signal Processing Using Approximate Adders,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 32, no. 1, pp. 124-137, 2013.
[CrossRef] [Google Scholar] [Publisher Link]
[3] Jie Han, and Michael Orshansky, “Approximate Computing: An Emerging Paradigm for Energy-Efficient Design,” 2013 18th IEEE European Test Symposium (ETS), Avignon, France, pp. 1-6, 2013.
[CrossRef] [Google Scholar] [Publisher Link]
[4] Z. Babić, A. Avramović, and P. Bulić, “An Iterative Logarithmic Multiplier,” Microprocessors and Microsystems, vol. 35, no. 1, pp. 2333, 2011.
[CrossRef] [Google Scholar] [Publisher Link]
[5] Rangharajan Venkatesan et al., “MACACO: Modeling and Analysis of Circuits for Approximate Computing,” 2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, USA, pp. 667-673, 2011.
[CrossRef] [Google Scholar] [Publisher Link]
[6] H.R. Mahdiani et al., “Bio-Inspired Imprecise Computational Blocks for Efficient VLSI Implementation of Soft-Computing Applications,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 57, no. 4, pp. 850-862, 2010.
[CrossRef] [Google Scholar] [Publisher Link]
[7] Farzad Farshchi, Muhammad Saeed Abrishami, and Sied Mehdi Fakhraie, “New Approximate Multiplier for Low Power Digital Signal Processing,” The 17th CSI International Symposium on Computer Architecture & Digital Systems (CADS 2013), Tehran, Iran, pp. 25-30, 2013.
[CrossRef] [Google Scholar] [Publisher Link]
[8] Parag Kulkarni, Puneet Gupta, and Milos Ercegovac, “Trading Accuracy for Power with an Underdesigned Multiplier Architecture,” 2011 24th Internatioal Conference on VLSI Design, Chennai, India, pp. 346-351, 2011.
[CrossRef] [Google Scholar] [Publisher Link]
[9] D.R. Kelly, B.J. Phillips, and S. Al-Sarawi, “Approximate Signed Binary Integer Multipliers for Arithmetic Data Value Speculation,” Proceedings of the 2009 Conference on Design & Architectures For Signal And Image Processing, pp. 97-104, 2009.
[Google Scholar] [Publisher Link]
[10] Khaing Yin Kyaw, Wang Ling Goh, and Kiat Seng Yeo, “Low-Power High-Speed Multiplier for Error-Tolerant Application,” 2010 IEEE International Conference of Electron Devices and Solid-State Circuits (EDSSC), Hong Kong, China, pp. 1-4, 2010.
[CrossRef] [Google Scholar] [Publisher Link]
[11] Amir Momeni et al., “Design and Analysis of Approximate Compressors for Multiplication,” IEEE Transactions on Computers, vol. 64, no. 4, pp. 984-994, 2015.
[CrossRef] [Google Scholar] [Publisher Link]
[12] Kartikeya Bhardwaj, and Pravin S. Mane, “ACMA: Accuracy-Configurable Multiplier Architecture for Error-Resilient System-on-Chip,” 2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), Darmstadt, Germany, pp. 1-6, 2013.
[CrossRef] [Google Scholar] [Publisher Link]
[13] Kartikeya Bhardwaj, Pravin S. Mane, and Jörg Henkel, “Power and Area-Efficient Approximate Wallace Tree Multiplier for ErrorResilient Systems,” Fifteenth International Symposium on Quality Electronic Design, Santa Clara, USA, pp. 263-269, 2014.
[CrossRef] [Google Scholar] [Publisher Link]
[14] John N. Mitchell, “Computer Multiplication and Division Using Binary Logarithms,” IRE Transactions on Electronic Computers, vol. EC-11, no. 4, pp. 512-517, 1962.
[CrossRef] [Google Scholar] [Publisher Link]
[15] V. Mahalingam, and N. Ranganathan, “Improving Accuracy in Mitchell’s Logarithmic Multiplication Using Operand Decomposition,” IEEE Transactions on Computers, vol. 55, no. 12, pp. 1523-1535, 2006.
[CrossRef] [Google Scholar] [Publisher Link]
[16] Srinivasan Narayanamoorthy et al., “Energy-Efficient Approximate Multiplication for Digital Signal Processing and Classification Applications,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 23, no. 6, pp. 1180-1184, 2015.
[CrossRef] [Google Scholar] [Publisher Link]
[17] Soheil Hashemi, R. Iris Bahar, and Sherief Reda, “DRUM: A Dynamic Range Unbiased Multiplier for Approximate Applications,” 2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Austin, USA, 2015, pp. 418-425, 2015.
[CrossRef] [Google Scholar] [Publisher Link]
[18] Chia-Hao Lin, and Ing-Chao Lin, “High Accuracy Approximate Multiplier with Error Correction,” 2013 IEEE 31st International Conference on Computer Design (ICCD), Asheville, USA, pp. 33-38, 2013.
[CrossRef] [Google Scholar] [Publisher Link]
[19] Cong Liu, Jie Han, and Fabrizio Lombardi, “A Low-Power, High-Performance Approximate Multiplier with Configurable Partial Error Recovery,” 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE), Dresden, Germany, pp. 1-4, 2014.
[CrossRef] [Google Scholar] [Publisher Link]