Low Latent Fixed Width Multiplier for Error Resilient Computation
International Journal of Electrical and Electronics Engineering |
© 2024 by SSRG - IJEEE Journal |
Volume 11 Issue 6 |
Year of Publication : 2024 |
Authors : B.V. Srividya, S.P. Meharunnissa, Chetan Umadi, Nagarathna, Saravana Kumar |
How to Cite?
B.V. Srividya, S.P. Meharunnissa, Chetan Umadi, Nagarathna, Saravana Kumar, "Low Latent Fixed Width Multiplier for Error Resilient Computation," SSRG International Journal of Electrical and Electronics Engineering, vol. 11, no. 6, pp. 182-187, 2024. Crossref, https://doi.org/10.14445/23488379/IJEEE-V11I6P120
Abstract:
Many applications in signal processing have an innate ability to tolerate a certain amount of computational mistakes. The human eye’s limited capacity for perceiving images and videos makes approximation useful in computations. Hence, this concept of error resilience approach can be accommodated in the hardware to reduce the computational time in high-speed circuits. Basically, multiplication in the signal processing domain takes a longer time. Hence, approximate multipliers have been an area of interest in recent times. This paper initially deals with a detailed study of various approaches to approximate multipliers. Subsequently, a novel architecture for error-resilient multiplication is proposed wherein approximate partial products are obtained. The entire multiplication operation is divided into three modules. The architecture of these modules is designed such that it provides the approximate output. These three modules work in parallel, thereby increasing the throughput. Efficient components are used in the design to improve the performance. The proposed multiplier is designed and simulated using Cadence 45nm technology.
Keywords:
Error resilience, Fixed width multipliers, Signal processing, Throughput, Low latency.
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