Design and FPGA Implantation of SoC for Multimedia Applications Using Deep Learning Based RNN Architecture for Low Power and High Throughput

International Journal of Electrical and Electronics Engineering

© 2024 by SSRG - IJEEE Journal

Volume 11 Issue 7

Year of Publication : 2024

Authors : B.N. Mohankumar, M.S. Kusuma, H.V. Pallavi, U. Rajashekhar, Neelappa

10.14445/23488379/IJEEE-V11I7P109

How to Cite?

B.N. Mohankumar, M.S. Kusuma, H.V. Pallavi, U. Rajashekhar, Neelappa, "Design and FPGA Implantation of SoC for Multimedia Applications Using Deep Learning Based RNN Architecture for Low Power and High Throughput," SSRG International Journal of Electrical and Electronics Engineering, vol. 11,  no. 7, pp. 113-123, 2024. Crossref, https://doi.org/10.14445/23488379/IJEEE-V11I7P109

Abstract:

Machine Learning (ML) techniques have become pivotal in the realms of customized integrated circuits are essential components in modern electronics, with two prominent types being ASICs and FPGAs, particularly in applications such as driverless vehicles, automotive electronics and big data analysis, where speed, power efficiency, and accuracy are paramount. This paper acknowledges a novel reconstructed hardware architecture at the SOC system level, including M33 processor and security to transfer steaming packets between processor and peripherals to meet the demands of modern ASIC and FPGA designs, offering high accuracy, low power consumption and increased throughput. The proposed system integrates an MLbased Support Vector Machine (SVM) with a fast-moving Advanced High-performance Bus (AHB) protocol, Floating Point (FP) operations, and support for I2C and I2S communication protocols. To enhance throughput and minimize latency, an AHB protocol and AHB to Advanced Peripheral Bus (APB) bridge have been implemented along with security algorithms, including SHA-256 and AES that are integrated into the vigorously reconstructed multi-processor. For Deep Learning (DL) - Recurrent Neural Networks (RNNs) based utilities, the system incorporates “Double-Precision Floating-Point (DPFP)” arithmetic operations. Design is implemented in Verilog HDL, which undergoes quality checks using the LINT tool and “Clock Domain Crossing (CDC)” analysis using Spyglass. Synthesis is carried out using a DC compiler for ASIC and Vivado Design Suite 2018 for FPGA execution and examination. The design architecture is connected with the SDK tool and Zynq processor to analyse data transmitted between software along hardware. Experimental outputs demonstrate that the custom accelerator can efficiently compute difficult ML classifiers for large datasets. Compared to state-of-the-art results, the proposed architecture offers a 24% improvement in outturn, a 27% scaling down in power consumption, and a 32% decrease in latency.

Keywords:

AHB, APB, SVM, I2C, I2S, RNN, DPFP, SoC.

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