Design of High-Speed Low Power 4-bit ALU Using CNTFET
| International Journal of Electrical and Electronics Engineering |
| © 2024 by SSRG - IJEEE Journal |
| Volume 11 Issue 8 |
| Year of Publication : 2024 |
| Authors : B. Anjaneyulu, N. Siva Sankara Reddy |
10.14445/23488379/IJEEE-V11I8P104
How to Cite?
B. Anjaneyulu, N. Siva Sankara Reddy, "Design of High-Speed Low Power 4-bit ALU Using CNTFET," SSRG International Journal of Electrical and Electronics Engineering, vol. 11, no. 8, pp. 36-49, 2024. Crossref, https://doi.org/10.14445/23488379/IJEEE-V11I8P104
Abstract:
As the electronic semiconductor sector undergoes downsizing, there are many challenges, including scaling, short-channel impacts, leakage currents and stability. Carbon Nanotubes (CNT) have emerged as an exciting new invention that can overcome the limitations of CMOS while maintaining high efficiency and dependability. The Arithmetic and Logical Unit (ALU) is the central operational programmable logic component that exists in microprocessors, and real-time computer chips. Traditional Arithmetic Logic Units (ALUs) were created utilizing CMOS technology, leading to high power usage, delays, as well as transistor count. This article specifically addresses the conceptualization and development of a hybrid Arithmetic Logic Unit (ALU) employing Carbon Nanotube Field-Effect Transistors (CNTFET). First, a combination of XOR and MUX is developed, which is then utilized to create hybrid adders and subtractors. The study showcases the development, simulation, and evaluation of an enhanced Arithmetic Logic Unit (ALU) utilizing Carbon Nanotube (CNT) technology and compares it to a traditional CMOS implementation using 32 nm technology nodes. The ALU that utilizes Carbon Nanotube (CNT) technology showed higher performance with regard to power usage, propagation delay, and the Power-Delay Product (PDP) when compared to its counterparts depending on CMOS technology.
Keywords:
CNTFET, ALU, Power, Delay, CMOS, Short-channel impacts.
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