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Realization of Trinary Asymmetrical Nine Level Reduced Switch Count Multi Level Inverter

International Journal of Electrical and Electronics Engineering
© 2024 by SSRG - IJEEE Journal
Volume 11 Issue 8
Year of Publication : 2024
Authors : Rumana Abideen, Donapati Ramakrishna Reddy
10.14445/23488379/IJEEE-V11I8P110
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How to Cite?

Rumana Abideen, Donapati Ramakrishna Reddy, "Realization of Trinary Asymmetrical Nine Level Reduced Switch Count Multi Level Inverter," SSRG International Journal of Electrical and Electronics Engineering, vol. 11,  no. 8, pp. 112-120, 2024. Crossref, https://doi.org/10.14445/23488379/IJEEE-V11I8P110

Abstract:

The popularity of Multilevel Inverters (MLIs) for obtaining high-power conversion due to their low voltage stress across power switches and low total harmonic distortion in output voltage waveform has emerged enormously. Thus, a trinary asymmetrical module based 9-level RSC-MLI is proposed in this work. By the replacement of a few bidirectional switches with unidirectional switches, the number of semiconductor devices is reduced. Due to this, voltage stress across each switch is reduced. In addition to this low Total Harmonic Distortion and improved efficiency with Zero Voltage Switching operation. The ease of control and implementation is assessed using a reduced carrier pulse width modulation technique, which overcomes limitations of other schemes such as the number of carriers, number of comparators, and total harmonic distortion. Additionally, the superiority of the proposed asymmetrical module over the literature reported is evidenced based on switching losses, redundancy and efficiency. Simulation is carried out on MATLAB/SIMULINK R2020(b). Finally, the simulation results demonstrate the reliability of the proposed design.

Keywords:

Alternate phase disposition, In phase disposition, Cascaded H-Bridge, Flying Capacitor, Multilevel Inverter, Opposite phase disposition, Reduced switch count, Phase shifted pulse width modulation.

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