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Design and analysis of Delay Controllable Reconfiguration ALU Using FinFET and CNTFET

International Journal of Electrical and Electronics Engineering
© 2024 by SSRG - IJEEE Journal
Volume 11 Issue 12
Year of Publication : 2024
Authors : B. Anjaneyulu, N. Siva Sankara Reddy
10.14445/23488379/IJEEE-V11I12P118
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How to Cite?

B. Anjaneyulu, N. Siva Sankara Reddy, "Design and analysis of Delay Controllable Reconfiguration ALU Using FinFET and CNTFET," SSRG International Journal of Electrical and Electronics Engineering, vol. 11,  no. 12, pp. 196-207, 2024. Crossref, https://doi.org/10.14445/23488379/IJEEE-V11I12P118

Abstract:

The Arithmetic and Logical Unit (ALU) is the central functional programmable logic block in real-time ICs. Traditional Arithmetic Logic Units (ALUs) have been developed utilizing CMOS technological devices, leading to high power usage, delays in processing, and many devices. This work addresses the conceptualisation and subsequent investigation of a delay-controllable reconfiguration ALU using FinFET and CNTFET technologies. The first development entails the establishment of a novel COPFA and CISFA using multiplexing selection circuitry. Consequently, these adders are used to create delay-controllable adders and delay-controllable subtractors. The Delay controllable reconfiguration ALU can be generated by incorporating the arithmetic and logical functions. The computational findings demonstrate that the suggested nanotechnology-based designs surpassed the traditional adders and subtractors regarding reducing power and latency. The power consumption of the proposed CNTFET 4-bit ALU is atleast 32% lower than that of the existing 4-bit ALUs. The delay period of the CNTFET4-bit proposed ALU has been reduced by 50% compared to the existing ALUs.

Keywords:

ALU, Power usage, Delay, FinFET, CNTFET, Reconfigurable adders.

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