A Physical LDMOST Model and Predictive Simulations for Advanced Technology CAD

International Journal of Electrical and Electronics Engineering
© 2025 by SSRG - IJEEE Journal
Volume 12 Issue 2
Year of Publication : 2025
Authors : Yeonbae Chung
pdf
How to Cite?

Yeonbae Chung, "A Physical LDMOST Model and Predictive Simulations for Advanced Technology CAD," SSRG International Journal of Electrical and Electronics Engineering, vol. 12,  no. 2, pp. 39-47, 2025. Crossref, https://doi.org/10.14445/23488379/IJEEE-V12I2P105

Abstract:

This article describes a compact Lateral DMOS Transistor (LDMOST) model incorporated directly into SPICE source code and presents its application to power IC technology CAD. The complete model combines a previously developed semi-numerical static model and a built-in parasitic component model with a charge-based dynamic model. This composite model is based on device physics; thus, it accounts well for important power MOSFET characteristics such as non-uniformly doped channels, reverse-recovery transients and the non-planar drift region. The measurements from the power MOSFET samples support the predictive model, verified in extensive SPICE simulations of several high-voltage circuits. This LDMOST model might be useful in computer-aided optimal design of smart power ICs.

Keywords:

Charge-based dynamic model, High-voltage MOSFET, Lateral DMOS transistor, Parasitic BJT model, Power IC technology CAD.

References:

[1] Bruno Murari, Franco Bertotti, and Guiovanni A. Vignola, Smart Power ICs: Technologies and Applications, 1st ed., Springer Berlin, Heidelberg, 2002.
[Google Scholar] [Publisher Link]
[2] M.D. Pocha, and R.W. Dutton, “A Computer-Aided Design Model for High-Voltage Double Diffused MOS (DMOS) Transistors,” IEEE Journal of Solid-State Circuits, vol. 11, no. 5, pp. 718-726, 1976.
[CrossRef] [Google Scholar] [Publisher Link]
[3] H.R. Claessen, and P. Van Der Zee, “An Accurate DC Model for High-Voltage Lateral DMOS Transistors Suited for CACD,” IEEE Transactions on Electron Devices, vol. 33, no. 12, pp. 1964-1970, 1986.
[CrossRef] [Google Scholar] [Publisher Link]
[4] R.S. Scott, G.A. Franz, and J.L. Johnson, “An Accurate Model for Power DMOSFET’s Including Interelectrode Capacitances,” IEEE Transactions on Power Electronics, vol. 6, no. 2, pp. 192-198, 1991.
[CrossRef] [Google Scholar] [Publisher Link]
[5] M.Y. Hong, and D.A. Antoniadis, “Theoretical Analysis and Modeling of Submicron Channel Length DMOS Transistors,” IEEE Transactions on Electron Devices, vol. 42, no. 9, pp. 1614-1622, 1995.
[CrossRef] [Google Scholar] [Publisher Link]
[6] A.C.T. Aarts, and W.J. Kloosterman, “Compact Modeling of High-Voltage LDMOS Devices Including Quasi-Saturation,” IEEE Transactions on Electron Devices, vol. 53, no. 4, pp. 897-902, 2006.
[CrossRef] [Google Scholar] [Publisher Link]
[7] Avinash S. Kashyap et al., “Compact Modeling of LDMOS Transistors for Extreme Environment Analog Circuit Design,” IEEE Transactions on Electron Devices, vol. 57, no. 6, pp. 1431-1439, 2010.
[CrossRef] [Google Scholar] [Publisher Link]
[8] Y.S. Kim, and J.G. Fossum, “Physical DMOST Modeling for High-Voltage IC CAD,” IEEE Transactions on Electron Devices, vol. 37, no. 3, pp. 797-803, 1990.
[CrossRef] [Google Scholar] [Publisher Link]
[9] Y.S. Kim, J.G. Fossum, and R.K. Williams, “New Physical Insights and Models for High-Voltage LDMOST IC CAD,” IEEE Transactions on Electron Devices, vol. 38, no. 7, pp. 1641-1649, 1991.
[CrossRef] [Google Scholar] [Publisher Link]
[10] J. Paredes et al., “A Steady-State VDMOS Transistor Model,” IEEE Transactions on Electron Devices, vol. 39, no. 3, pp. 712-719, 1992.
[CrossRef] [Google Scholar] [Publisher Link]
[11] J.J. Victory et al., “A Static, Physical VDMOS Model Based on the Charge-Sheet Model,” IEEE Transactions on Electron Devices, vol. 43, no. 1, pp. 157-164, 1996.
[CrossRef] [Google Scholar] [Publisher Link]
[12] C.W. Tang, and K.Y. Tong, “A Compact Large Signal Model of LDMOS,” Solid-State Electronics, vol. 46, no. 12, pp. 2111-2115, 2002.
[CrossRef] [Google Scholar] [Publisher Link]
[13] A. Aarts, N. D’Halleweyn, and R. van Langevelde, “A Surface-Potential-Based High-Voltage Compact LDMOS Transistor Model,” IEEE Transactions on Electron Devices, vol. 52, no. 5, pp. 999-1007, 2005.
[CrossRef] [Google Scholar] [Publisher Link]
[14] Yeonbae Chung, and Taehoon Kim, “A Steady-State LDMOST Model Based on Semi-Numerical Regional Approach,” International Journal of Emerging Technology and Advanced Engineering, vol. 12, no. 9, pp. 94-101, 2022.
[CrossRef] [Google Scholar] [Publisher Link]
[15] H.K. Gummel, and H.C. Poon, “An Integral Charge Control Model of Bipolar Transistors,” The Bell System Technical Journal, vol. 49, no. 5, pp. 827-852, 1970.
[CrossRef] [Google Scholar] [Publisher Link]
[16] J.G. Fossum, and M.A. Shibib, “An Analytic Model for Minority-Carrier Transport in Heavily Doped Regions of Silicon Devices,” IEEE Transactions on Electron Devices, vol. 28, no. 9, pp. 1018-1025, 1981.
[CrossRef] [Google Scholar] [Publisher Link]
[17] Soo-Young Oh, D.E. Ward, and R.W. Dutton, “Transient Analysis of MOS Transistors,” IEEE Journal of Solid-State Circuits, vol. 15, no. 4, pp. 636-643, 1980.
[CrossRef] [Google Scholar] [Publisher Link]
[18] Laurence W. Nagel, “SPICE2: A Computer Program to Simulate Semiconductor Circuits,” Technical Report No. UCB/ERL M520, Electronics Research Laboratory, University of California, Berkeley, CA, 1975.
[Google Scholar] [Publisher Link]
[19] A.R. Hefner, “An Improved Understanding for the Transient Operation of the Power Insulated Gate Bipolar Transistor (IGBT),” IEEE Transactions on Power Electronics, vol. 5, no. 4, pp. 459-468, 1990.
[CrossRef] [Google Scholar] [Publisher Link]