SSRG International Journal of VLSI & Signal Processing
( IJVSP )

Editor in Chief	Prof. Dr. Abu Khari Bin A'Ain,
	Electronics Engineering,
	University of Technology Malaysia,
	Malaysia.
ISSN	2394-2584
Publication Frequency	3 Issue per Year
Publisher	Seventh Sense Research Group®
Paper Submission id	ijvsp@ssrgjournals.org

SSRG International Journal of VLSI & Signal Processing ( SSRG - IJVSP ) is a scholarly double-blind peer-reviewed research publishing Journal.

Aim and Scope:

SSRG International Journal of VLSI & Signal Processing - IJVSP publishes research and survey papers on the design and implementation of signal processing systems with VLSI circuits. It is distributed to engineers, researchers and educators in the fields of VLSI design and signal processing. The key subject areas of interest to the journal of VLSI Signal Processing are: design and analysis of signal processing algorithms and architecture performance analysis (including measurement modeling and simulation) of signal processing systems VLSI design methodology (including silicon compilation) design of arithmetic circuits and VLSI components used in signal processing (such as multipliers dividers and digital filter sections) specialized number systems (including on-line arithmetic residue number systems and logarithmic number systems) application of advanced technology (e.g. WSI ECL GaAs etc.) to signal processing generic and programmable processors special purpose signal processor architectures (including parallel and pipelined signal processors) systolic/wave front arrays neural nets.

IJVSP is a double blind peer reviewed International Journal that publishes articles which contribute new results in all areas of VLSI Design & Signal Processing. The goal of this journal is to bring together researchers and practitioners from academia and industry to focus on advanced VLSI Design & Signal Processing concepts and establishing new collaborations in these areas also: Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels.

Papers are solicited from, but not limited to the following topics:

Authors Geographical Coverage :

USA, Iraq, Pakistan, Nigeria, India, Korea, Syria, etc.