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Design and Simulation of 4*1 Mux Based on Low Power Design Techniques

International Journal of VLSI & Signal Processing
© 2015 by SSRG - IJVSP Journal
Volume 2 Issue 1
Year of Publication : 2015
Authors : Ira Parashar,Preeti Sikarwar, Rashmi Singh, Soumya Chauhan and Mrs. Shivani Saxena
10.14445/23942584/IJVSP-V2I1P105
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How to Cite?

Ira Parashar,Preeti Sikarwar, Rashmi Singh, Soumya Chauhan and Mrs. Shivani Saxena, "Design and Simulation of 4*1 Mux Based on Low Power Design Techniques," SSRG International Journal of VLSI & Signal Processing, vol. 2,  no. 1, pp. 17-21, 2015. Crossref, https://doi.org/10.14445/23942584/IJVSP-V2I1P105

Abstract:

In today’s scenario low power, speed and area efficient design has become one of the focuses in both analog and digital VLSI circuits. In this project, we design and simulate 4*1 multiplexer using different low power techniques namely Gate Diffusion Input (GDI), Dual Pass Transistor Logic(DPTL),Adiabatic Logic, Energy Charge Recovery Logic(ECRL), Transmission Gate. We also done a comparative study with conventional CMOS design on the basis of Transistor count, Speed, Power dissipation and Area .Cadence tools is used for simulation.

Keywords:

Adiabatic, CMOS, DPTL ,ECRL Power Dissipation, Speed, Transistor Count.

References:

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