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FPGA Implementation of Simple and High Speed Vedic Multiplier

International Journal of VLSI & Signal Processing
© 2015 by SSRG - IJVSP Journal
Volume 2 Issue 2
Year of Publication : 2015
Authors : Shilpi Thawait and Jagveer Verma
10.14445/23942584/IJVSP-V2I2P102
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How to Cite?

Shilpi Thawait and Jagveer Verma, "FPGA Implementation of Simple and High Speed Vedic Multiplier," SSRG International Journal of VLSI & Signal Processing, vol. 2,  no. 2, pp. 6-9, 2015. Crossref, https://doi.org/10.14445/23942584/IJVSP-V2I2P102

Abstract:

Multiplier is the basic and the key element used in many Digital Signal Processing applications, arithmetic operations, in image processing applications such as FFT (fast fourier transform), convolution, correlation etc. This paper presents a simplified and efficient method of multiplication using vedic mathematics. Vedic mathematics is the name given to the ancient Indian system of mathematics and is based on mental calculations. Urdhva Triyakbhyam sutra of vedic multiplication is found to be the most efficient sutra of vedic multiplication among its all 16 sutras. The aim of this paper is to implement a simpler and high speed vedic multiplier by using Urdhva Triyakbhyam sutra efficiently. Synthesis has been done using Xilinx ISE 9.2i simulator using VHDL language

Keywords:

CSA(Carry Save Adder), ISE (Integrated Software Environment), LUT (Look Up Table), UT(Urdhva-triyakbhyam), Vedic Multiplier, VHDL(Very High Speed Integrated Circuit Hardware Description Language), Xilinx.

References:

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[6] Wikipedia, http://en.wikipedia.org/wiki/Carry-save_adder, DOB- 29/04/2015.