Layout Design, Analysis and Implementation of Combinational and Sequential Circuits using Microwind

International Journal of VLSI & Signal Processing

© 2015 by SSRG - IJVSP Journal

Volume 2 Issue 2

Year of Publication : 2015

Authors : Ms.Amrita Pahadia and Dr. Uma Rathore Bhatt

10.14445/23942584/IJVSP-V2I2P108

How to Cite?

Ms.Amrita Pahadia and Dr. Uma Rathore Bhatt, "Layout Design, Analysis and Implementation of Combinational and Sequential Circuits using Microwind," SSRG International Journal of VLSI & Signal Processing, vol. 2,  no. 2, pp. 48-56, 2015. Crossref, https://doi.org/10.14445/23942584/IJVSP-V2I2P108

Abstract:

To design and analyse various combinational and sequential circuits. In the present thesis we worked on 45nm and 90 nm technologies. Using afore mentioned technologies; the layout for various sequential and combinational circuits has been designed in microwind 3.5 version tool and DSCH software. We designed and analyze three combinational circuit viz. multiplexer, half adder, full adder, 4 bit barrel shifter and one sequential circuit viz. 4bit up down counter.The combinational and sequential circuits are implemented by the use of stick diagram layout designing method with microwind 3.5 version tool and DSCH software. In microwind we designed stick diagram layout and in DSCH we designed schematic diagram of all logic operation. Design of low power circuit with high speed is the essential priority of VLSI tech. For this we designed various circuits which provide optimum results. The 45 nm technology layout for basic building block (multiplexer in our case) of all the circuits has been designed in microwind 3.5 version tool and DSCH software. The simulation is also performed for 90 nm technology. Simulation results show that the proposed design for the afore mentioned circuits is greater in terms of power consumption, temperature sustainability, noise immunity and frequency as compared to existing designs.

Keywords:

Power consumption, Temperature, Packing Density

References:

[1] M. Morris Mano, R. Kime, “Logic and Computer Design Fundamentals”, Pearson Education, 2nd edition, 2001.
[2] N. Weste and D. Harris. “CMOS VLSI Design” ,A circuit and systems perspective, third edition,pearson education, 2007.
[3] Shih-Chieh Chang, Lukas P.P.P. van Ginneken, “Circuit Optimization by Rewiring”, IEEE Transaction on Computers, Vol. 48, No. 9, September 1999.
[4] Behzad Razavi, “Design of Analog CMOS Integrated Circuit”, Tata McGraw Hill Edition, year 2002.
[5] J. Musicer, "An Analysis of MOS Current Mode Logic for Low Power and High Performance Digital Logic", Research Project, Berkeley University, 
[6] Shubhajit Roy Chowdhury, Aritra Banerjee, Aniruddha Roy, Hiranmay Saha, “A high Speed 8 Transistor Full Adder Design using Novel 3 Transistor XOR Gates”, International Journal of Electrical and Computer Engineering 3:12 2008.
[7] S. Giri, N.saraswathi , “Implementation of combinational circuits using ternary multiplexer,”International journal of computational engineering research,ISSN:2250-3005
[8] Shen-fu Hsiao, Jia-Stang Yeh, and Da-Yen Chen, “High Performance Multiplexer Based Logic Synthesis Using Pass-transistor Logic”, Taylor & francis Group, VLSI Design, vol. 15(1), pp. 417-426, in year 2002.
[9] Y.thakur, R.mehra, A.sharma“CMOS design of area and power efficient multiplexer using tree toplology”, International journal of computer applications,volume 112-no 11 ,February 2015. technology-volume 3 issue3-2012.
[10] M.padmaja, V.N.V. satya prakash “Design of a multiplexer in multiple logic styles for low power VLSI”, International journal of computer trades and
[11] Michael J. Schulte and E. George Walters III, “Design alternatives for barrel shifters,” Proc. SPIE Advanced Signal Processing Algorithms, Architectures, and Implementations, pp. 436-447, 2002. 
[12] H. Thapliyal and N. Ranganathan, “Design of reversible sequential circuits optimizing quantum cost, delay and garbage outputs,” ACM Journal of Emerging Technologies in Computing Systems, vol. 6, no. 4, pp. 14:1–14:35, Dec. 2010.
[13] M. Janaki Rani ,S. Malarkann, leakage power reduction and analysis of CMOS sequential circuits, International Journal of VLSI design & communication Systems (VLSICS) ,vol.3, no.1, Feb.2012, pp.13-23.
[14] Philip E. Allen and Douglass R. Holber,”, CMOS Analog Circuit Design,” International 2nd edition, Oxford University Press.
[15] Stan M.R, “Long and fast Up/Down counters”, IEEE Tran. on Comp., July 98, pp722-735.