SPI Controller Core: Verification

International Journal of VLSI & Signal Processing

© 2015 by SSRG - IJVSP Journal

Volume 2 Issue 3

Year of Publication : 2015

Authors : Nidhi Gopal

10.14445/23942584/IJVSP-V2I5P101

How to Cite?

Nidhi Gopal, "SPI Controller Core: Verification," SSRG International Journal of VLSI & Signal Processing, vol. 2,  no. 3, pp. 1-6, 2015. Crossref, https://doi.org/10.14445/23942584/IJVSP-V2I5P101

Abstract:

This paper mainly deals with the study of Serial Peripheral Interface and logical Implementation through RTL, Synthesis and Simulation by making Test benches of various modules involved using Universal Verification Methodology. It is done with the help of Questasim 10.0b software. Further, output in both Batch and GUI Mode has been observed and discussed. Various test cases of SPI Protocol are taken into consideration, functional coverage, code coverage, and assertion coverage has been verified by synthesis of various blocks involved in top level architecture of SPI.

Keywords:

Questasim, RTL, SPI, Synthesis, Simulation, Testcases.

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