Reducing the Computation Time in Two’s Complement Multipliers

International Journal of VLSI & Signal Processing

© 2015 by SSRG - IJVSP Journal

Volume 2 Issue 3

Year of Publication : 2015

Authors : A. Hari Priya

10.14445/23942584/IJVSP-V2I3P103

How to Cite?

A. Hari Priya, "Reducing the Computation Time in Two’s Complement Multipliers," SSRG International Journal of VLSI & Signal Processing, vol. 2,  no. 3, pp. 13-17, 2015. Crossref, https://doi.org/10.14445/23942584/IJVSP-V2I3P103

Abstract:

To reduce the area of partial product array size and improve the speed which is generated by a radix-4Modified Booth Encoded Multiplier is used. This reduction is possible without any increase in the delay of the partialproduct generation stage. This reduction provides faster compression of the partial product array and regular layoutsin two’s complement multiplier. The proposed method is that the Radix-4 (Fixed-Width) Modified Booth Multipliersare used to achieve the low power and increase the speed by modifying the partial product matrix size. The Multiplierdesign implemented using Xilinx. The results based on a rough theoretical analysis and on logic synthesis showed itsefficiency in terms of both area and delay. It is compared with Radix-4 (short bit-width) Modified booth encoded Multiplier.

Keywords:

Multiplication, Modified Booth encoding, partial product array.

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