Design of Robust and power Efficient 8-Bit Ripple Carry Adder using Different Logic Styles

International Journal of VLSI & Signal Processing

© 2016 by SSRG - IJVSP Journal

Volume 3 Issue 2

Year of Publication : 2016

Authors : Mangayarkkarasi M and Joseph Gladwin S

10.14445/23942584/IJVSP-V3I3P101

How to Cite?

Mangayarkkarasi M and Joseph Gladwin S, "Design of Robust and power Efficient 8-Bit Ripple Carry Adder using Different Logic Styles," SSRG International Journal of VLSI & Signal Processing, vol. 3,  no. 2, pp. 1-7, 2016. Crossref, https://doi.org/10.14445/23942584/IJVSP-V3I3P101

Abstract:

The binary adders are key component in digital signal processors (DSP). These adders are crucial building blocks in very large scale integrated circuits. Its efficient implementation is highly important because a carry propagation involving all operand bits has to be performed. With the increasing level of device integration power became the predominant design goal for fast adders. Low power consumption and smaller area are some of the most important criteria for fabrication of DSP systems and high performance systems. In this paper we try to determine the best solution to this problem by comparing a few 8-bit Ripple Carry Adder (RCA) circuits implementation with Complementary, Dynamic, Constant Delay (CD) and Energy Efficient Constanta Delay (EE-CD) logic styles. The adders are simulated using MicroWind environment to find an efficient adder structure. To reduce the power consumption for low power applications an EECD logic style is proposed. When we compare the power consumption of all the adder logic style we find that Complementary logic style consume more power. The EE-CD logic style has better power consumption compared to all other logic styles.

Keywords:

CMOS, Ripple Carry Adder, Power Consumption, Complementary Logic, Dynamic Logic, Constant Delay Logic, Energy Efficient- Constant Delay Logic.

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