Design of a CMOS Multiplexer with Ultra Low Power using Current Mode Logic Technology

International Journal of VLSI & Signal Processing

© 2016 by SSRG - IJVSP Journal

Volume 3 Issue 2

Year of Publication : 2016

Authors : Dr.R.Carlo Novara and Mohamed Djemai

10.14445/23942584/IJVSP-V3I2P102

How to Cite?

Dr.R.Carlo Novara and Mohamed Djemai, "Design of a CMOS Multiplexer with Ultra Low Power using Current Mode Logic Technology," SSRG International Journal of VLSI & Signal Processing, vol. 3,  no. 2, pp. 8-12, 2016. Crossref, https://doi.org/10.14445/23942584/IJVSP-V3I2P102

Abstract:

Thecurrent mode logic (CML) function is widely used for the processdue to their lower output voltage slaplinked to the static CMOS circuits and also used for very fast current switching and discrepancy pair of transistors. In this paper proposed a new method for planning Ultra Low Power and wide energeticseries for multiplexing analog indicators. The method is purely designed for weak inversion region and also used for the(CML) circuit. The effective frequency and power consumption can be speckled by the bias current of the gates. The multiplexer strategyhires CMOS transistors areused for increasing the threshold voltage in the transmission gate signals. Thisschemereveals that the power dissipation is low and active range is high.The main applications of the data selector are signal multiplexing functions, data routing, digital signal converting, sign gating, and number system preparation.

Keywords:

current mode logic function, multiplexing analog signals, the transmission gate signals and data selector.

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