An enhanced fault tolerant system in the design of ALU using TMR technique

International Journal of VLSI & Signal Processing

© 2016 by SSRG - IJVSP Journal

Volume 3 Issue 3

Year of Publication : 2016

Authors : C.V.Akilan Ready and J.Diwakar patil

10.14445/23942584/IJVSP-V3I3P102

How to Cite?

C.V.Akilan Ready and J.Diwakar patil, "An enhanced fault tolerant system in the design of ALU using TMR technique," SSRG International Journal of VLSI & Signal Processing, vol. 3,  no. 3, pp. 8-14, 2016. Crossref, https://doi.org/10.14445/23942584/IJVSP-V3I3P102

Abstract:

Nowadays, the technology has been emerged at a peak on Nano dimension in the significant fields of industrial sectors. Meanwhile, the manufacturing process of the concerned system is much unreliable which would directly impact the production. Reliability is one of the significant aspects that have to be evaluated during the planning segment of any Integrated Circuits. Some of the most important applications like Medical and Military field, reliability plays a very crucial part in defining the recognition of product. Attachment of distinct elements in the main proposal for consistency improvement will give substantial quantity of area & power drawback. Consequently, fault tolerant approaches are suitably progressively essential, mainly in safety issues applications. Hence, a unique method is used to invent new ways for reclaiming the previously offered constituents in digital system. According to the system, ALU is a functional block of the central processing unit of a computer. So, it is vital that the system need to be fault free or fault tolerant. With the purpose of having high consistency and high accessibility of the system, used the standard Triple Modular Redundancy technique. This system is customarily used for defending digital logic from the single event upset by triplication the acute modules of the structure to give fault tolerance to system. The main concern of this paper is to attain less power consumption with high consistency while using any new methodologies to design the system.

Keywords:

  Fault tolerance, Triple Modular Redundancy technique, Reliability.

References:

[1] Tian Ban; LiridaAlves de Barros Naviner, ―A simple faulttolerant digital voter circuit in TMR Nano architectures, IEEE InternationalNEWCAS Conference (NEWCAS), Pages: 269 – 272, 2010
[2] AyonMajumdar; SahilNayyar; Jitendra Singh Sengar, ―Fault Tolerant ALU System, IEEE Conference on Computing Sciences (ICCS), Pages: 255 - 260, 2012
[3] R. V. Kshirsagar; R. M. Patrikar, ―A novel fault tolerant design and an algorithm for tolerating faults in digital circuits, IEEE 3rd International Design and Test Workshop, Pages: 148 - 153, 2008
[4] D. A. Tran; A. Virazel; A. Bosio; L. Dilillo; P. Girard; S. Pravossoudovitch; H. -J. Wunderlich, ―A Hybrid Fault Tolerant Architecture for Robustness Improvement of Digital Circuits, IEEE Conference on Asian Test Symposium , Pages: 136 - 141, 2011.
[5] Z. Stamenkovic; V. Petrovic, ―A comprehensive approach to fault tolerance: Device, circuit, and system techniques, 17th Latin-American Test Symposium (LATS), IEEE Conference Publications, Pages: 20 – 25, 2016.
[6] V. S. Veeravalli, Fault Tolerance for Arithmetic and Logic Unit, IEEE South eastcon, GA, Atlanta (2009) pp. 329-334.
[7] K. Matsumoto, M. Uehara and H. Mori, Evaluating the Fault Tolerance of Stateful TMR, in 13th International Conference on Network based Information Systems, Takayama (2010) pp. 332- 336.
[8] Ankit K V 1, S MuraliNarasimham 2 and Dr. ViajyaPrakash A M 3(2015)― Design approach for Fault Recoverable ALU with improved fault tolerance International Journal of VLSI design & Communication Systems (VLSICS) Vol.6, No.4, August 2015.
[9] A.J Goode, ―Design considerations for a single-chip fault tolerant VLSI microprocessor Software & Microsystems, Vol. 4, No. 3, June 1985
[10] J.Vial, A. Virazel, A. Bosio, P. Girard, C. Landrault, S. Pravossoudovitch, Is triple modular redundancy suitable for yield improvement?, IET Computer Digital Technology 3 (6) (2009) 581-592.
[11] N. M. Huu, B. Robisson, M. Agoyan and N. Drach, Lowcost fault tolerance on the ALU in simple pipelined processors, in IEEE 13th International Symposium on Design and Diagnostics of Electronics Circuits and Systems, Austria (2010) pp. 28-31.
[12] Deepti Shinghal1, Dinesh Chandra2, ―Design and Analysis of a Fault Tolerant Microprocessor Based on Triple Modular Redundancy Using VHDL, International Journal of Advances in Engineering & Technology, Mar 2011, IJAET.