Design of Second Order Adiabatic Logic for Energy Dissipation in VLSI CMOS Circuits

International Journal of VLSI & Signal Processing

© 2017 by SSRG - IJVSP Journal

Volume 4 Issue 1

Year of Publication : 2017

Authors : Sudhakar Alluri, B.Rajendra Naik and N.S.S.Reddy

10.14445/23942584/IJVSP-V4I1P103

How to Cite?

Sudhakar Alluri, B.Rajendra Naik and N.S.S.Reddy, "Design of Second Order Adiabatic Logic for Energy Dissipation in VLSI CMOS Circuits," SSRG International Journal of VLSI & Signal Processing, vol. 4,  no. 1, pp. 14-24, 2017. Crossref, https://doi.org/10.14445/23942584/IJVSP-V4I1P103

Abstract:

These circuits produce an energy savings of at most one order of dd t V V . This paper propose a novel class of adiabatic total circuits that fact offer several advantages over existing approaches, the prime one being that, because no diodes are used, switching energy can be decreased to an energy flooring of ( ) 2 t O CV . These second order adiabatic computing circuits produce an energy savings of as much as ( ) 2 dd t O V V over general CMOS. The proposed circuits have been simulated and determine adiabatic power savings compared to standard CMOS circuits over an performing frequency range from 1MHz to 100MHz using Cadence virtuoso tool at 45nm technology. We proposed a Basic 2N-2P differential buffer/inverter, 4-Phase shift register bit, Complex gate. Basic 2N-2N2P Inverter/Buffer Gate, adiabatic Full Adder using CADENCE EDA tool at 45nm technology.

Keywords:

Standard CMOS circuits, adiabatic full adder, low frequency, low power, Energy dissipation, ,Complex gate, 4-Phase shift register bit, VLSI.

References:

[1] Matthew Morrison, and Nagarajan Ranganathan," Synthesis of Dual-Rail Adiabatic Logic for Low Power Security Applications",IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 33, NO. 7, JULY 2014, 0278-0070 _c 2014 IEEE.
[2] Samer Houri, Gerard Billiot, Marc Belleville, Alexandre Valentian, and Hervé Fanet," Limits of CMOS Technology and Interest of NEMS Relays for Adiabatic Logic Applications",IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, 1549-8328 © 2015 IEEE.
[3] Irfan Ahmad Pindoo, Tejinder Singh, Amritpal Singh," Power Dissipation Reduction Using Adiabatic Logic Techniques for CMOS Inverter Circuit",6th ICCCNT - 2015 July 13 - 15, 2015, Denton, U.S.A,IEEE - 35239.
[4] Rolf Landauer, "Irreversibility and Heat Generation in the Computing Process", IBM J. Res. Devel. vol. 5pp. 183-191 (1961).
[5] C. H. Bennett,"Logical Reversibility of Computation", IBM J. Res. Devel. vol. 17, pp525-532 (1973).
[6] C. Seitz et al., "Hot Clock nMOS", Proceedings of the 1985 Chapel Hill Conference on VLSI. Computer Science Press (1985).
[7] Roderick T. Hinman and Martin F. Schlecht, "Power Dissipation Measurements on Recovered Energy Logic", 1994 Symposium on VLSI Circuits / Digest of Technical Papers, 19. IEEE (June 1994).
[8] A. G. Dickinson and J. S. Denker, "Adiabatic Dynamic Logic", Proceedings of the Custom Integrated Circuits Conference. IEEE (1994).
[9] J. G. Koller and W.C. Athas, "Adiabatic Switching, Low Energy Computing, and the Physics of Storing and Erasing Information", PhysComp '92: Proc. of the Workshop on Physics and Computation. IEEE (1993).
[10] Ralph C. Merkle, "Reversible Electronic Logic using Switches", Nanotechnology Vol. 4 21{40. (1993).
[11] Alan Kramer, John S. Denker, Stephen C. Avery, Alex G. Dickinson, and Thomas R. Wik, "Adiabatic Computing with the 2N-2N2D Logic Family", 1994 Symposium on VLSI Circuits / Digest of Technical Papers,25. IEEE (June 1994).
[12] J. S. Hall, "An Electroid Switching Model for Reversible Computer Architectures", Phys Comp '92: Proc. of the Workshop on Physics and Computation. IEEE (1993).
[13] S. G. Younis and T. Knight, "Practical Implementation of Charge Recovering Asymptotically Zero Power CMOS", Proc. of 1993 Symposium on Integrated Systems, 234{250. MIT Press (1993).
[14] T.J. Gabara, "Pulsed Low Power CMOS", Inter. J. of High Speed Elec. and Systems, Vol. 5 2, (1994).
[15] Y. Van Rentergem and A. De Vos, ―Optimal design of a reversible full adder, in Proc. Int. J. Unconventional Comput., 2005, pp. 339–345.
[16] A. De Vos, Reversible Computing. Weinheim: Wiley-VCH, 2010.
[17] V. V. Zhirnov, R. K. Cavin, J. A. Hutchby, and G. I. Bourianoff, ―Limits to binary logic switch scaling: A Gedanken model, Proc. IEEE, vol. 91, no. 11, pp. 1934–1939, Nov. 2003.
[18] K. Cavin, V. V. Zhirnov, J. A. Hutchby, and G. I. Bourianoff, ―Energy barriers, demons, and minimum energy operation of electronic devices, in Proc. Fluct. Noise Lett., Austin, TX, USA, 2005.
[19] G. P. Boechler, J. M. Whitney, C. S. Lent, A. O. Orlov, and G. L. Snider, ―Fundamental limits of energy dissipation in chargebased computing, Appl. Phys. Lett., vol. 97, no. 10, pp. 103502– 103503, Sep. 2010.
[20] V. V. Zhirnov and R. K. Cavin, ―Comment on ‘Fundamental limits of energy dissipation in charge-based computing‘, Appl. Phys. Lett., vol. 98, no 9, 2010.
[21] G. P. Boechler, J. M. Whitney, C. S. Lent, A. O. Orlov, and G. L. Snider, ―Response to Comment on ‗Fundamental limits of energy dissipation in charge-based computing‘, Appl. Phys. Lett., vol. 98, no. 9, pp. 096102–096102-1, 2011.
[22] G. L. Snider et al., ―Minimum energy for computation, theory vs.experiment, in Proc. IEEE-NANO, Portland, OR, USA, Aug. 2011, pp. 478–481.
[23] R. Puri, ―Opportunities and challenges for high performance microprocessor designs and design automation, in Proc. ACM ISPD, New York, NY, USA, 2013, p. 179.
[24] Y. Moon and D. K. Jeong, ―An efficient charge recovery logic circuit, IEEE J. Solid State Circuits, vol. 31, no. 4, pp. 514–522, Apr. 1996.
[25] M. Saeed and I. Markov, ―Synthesis and optimization of reversible circuits—A survey, ACM CSUR, vol. 45, no. 2, Article 21, Feb. 2013.
[26] D. Sokolov, J. Murphy, A. Bystrov, and A. Yakovlev, ―Design and analysis of dual-rail circuits for security applications, IEEE Trans. Comput., vol. 54, no. 4, pp. 449–460, Apr. 2005.
[27] H. Saputra et al., ―Masking the energy behaviour of DES encryption, in Proc. DATE, Munich, Germany, 2003, pp. 84–89.
[28] Y. Zeng et al., ―A low-power Rijndael S-Box based on pass transmission gate and composite field arithmetic, J. Zhejiang Univ. Sci. A, vol. 8, no. 10, pp. 1553–1559, 2007.
[29] J. Wolkerstorfer, E. Oswald, and M. Lamberger, ―An ASIC implementation of the AES S-Boxes, in Proc. CT-RSA, San Jose, CA, USA, 2002, pp. 67–78.
[30] K. Tiri and I. Verbauwhede, ―A logic level design methodology for a secure DPA-resistant ASIC or FPGA implementation, in Proc. DATE, Paris, France, 2004, pp. 246–251.
[31] V. Sundaresan, S. Rammohan, and R. Vemuri, ―Power invariant secure- IC design methodology using reduced complementary dynamic and differential logic, in Proc. VLSI, Atlanta, GA, USA, 2007, pp. 1–6.
[32] M. Rostami et al., ―Balancing security and utility in medical devices? in Proc. DAC, Austin, TX, USA, 2013, p. 13.
[33] C. Wang and N. M. Heys, ―Using a pipelined S-box in compact AES hardware implementations, in Proc. 8th IEEE NEWCAS, Montreal, QC, Canada, Jun. 2010, pp. 101–104.
[34] J. Mathew, H. Rahaman, A. M. Jabir, S. P. Mohanty, and D. K. Pradhan, ―On the design of different concurrent EDC schemes for S-Box and GF(p), in Proc. ISQED, Mar. 2010, pp. 211–218.
[35] C. Monteiro, Y. Takahashi, and T. Sekine, ―Low power secure AES S-box using adiabatic logic circuit, in Proc. IEEE FTFC, Paris, France, Jun. 2013, pp. 1–4.
[36] P. Hämäläinen, T. Alho, M. Hännikäinen, and T. D. Hämäläinen, ―Design and implementation of low-area and lowpower AES encryption hardware core, in Proc. 9th EUROMICRO Conf. DSD, Dubrovnik, Croatia, Aug. 2006, pp. 577–583.