Realisation of Vedic sutras for multiplication in Verilog

International Journal of VLSI & Signal Processing

© 2017 by SSRG - IJVSP Journal

Volume 4 Issue 1

Year of Publication : 2017

Authors : A. Kamaraj, A. Daisy Parimalah and V. Priyadharshini

10.14445/23942584/IJVSP-V4I2P106

How to Cite?

A. Kamaraj, A. Daisy Parimalah and V. Priyadharshini, "Realisation of Vedic sutras for multiplication in Verilog," SSRG International Journal of VLSI & Signal Processing, vol. 4,  no. 1, pp. 25-29, 2017. Crossref, https://doi.org/10.14445/23942584/IJVSP-V4I2P106

Abstract:

This project involves application of the Sutras to design a 8*8multiplier circuit based on Vedas. Mathematics, derived from the Vedas, provides one line, mental and superfast methods along with quick cross checking systems.In this Project, four different multiplication sutras are considered, namely, Ekanyunena Purvena, Anurupyena, Antyayor-Dasakepi, Urdhva- Tiryagbhyam for multiplication process. Each multiplication sutras are having their own unique features to determine the product terms. An adaptive multiplication unit will be designed which consists of all these four sutras and a control unit. The intelligent control unit dynamically invokes the suitable multiplication algorithm based on the input data. The final Product will be available in minimum delay with optimized area. The entire hardware including the control unit is designed using Verilog and it is to be implemented in FPGA.

Keywords:

Ekanyunena Purvena, Anurupyena, Antyayor Dasakepi, Urdhva Tiryagbhyam, Vedic mathematics.

References:

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