High-Speed and Energy-Efficient Carry Skip Adder functioning under a extensive range of supply voltage Levels

International Journal of VLSI & Signal Processing

© 2017 by SSRG - IJVSP Journal

Volume 4 Issue 2

Year of Publication : 2017

Authors : Amrutavarshini S H and Mr. S Pramod Kumar

10.14445/23942584/IJVSP-V4I3P101

How to Cite?

Amrutavarshini S H and Mr. S Pramod Kumar, "High-Speed and Energy-Efficient Carry Skip Adder functioning under a extensive range of supply voltage Levels," SSRG International Journal of VLSI & Signal Processing, vol. 4,  no. 2, pp. 1-5, 2017. Crossref, https://doi.org/10.14445/23942584/IJVSP-V4I3P101

Abstract:

In this paper, we herein present a structure of adder which has higher speed yet lower energy at consumption which when compared with the conventional one. The speed of the enhancement is achieved by applying the concatenation and the scheme of incrementation to ameliorate the efficiency of the conventional CSKA structure. Instead premeditating on the multiplexer logic, suggested structure makes utilization of AND-OR-Invert or AOI and OR-AND-Invert compound gates for those skip logic. The whole structure may be realized with both fixed stage size and also variable style in size wherein the latter furthering augments the speed and the respective parameters of energy of the corresponding adder. Ultimately, hybrid variable latency at extension of the suggested structure, which lessens the utilization of the power without making an impact at the speed which is representing a speed. This extension utilizes the amended parallel type structure basically for augmenting the feeble time thus capacitating at the further reduction of voltage. Suggested structure are assessed by making a comparison of their speed, power and parameters of energy with those of other type adders utilizing a forty nm static CMOS in technology for an extensive range of supply of voltage.

Keywords:

Carry skip adder(CSKA), Ripple Carry adder(RCA).

References:

[1] S. Turrini, “Optimal group distribution in carry-skip adders,” in Proc. 9th IEEE Symp. Comput. Arithmetic, Sep. 1989, pp. 96–103.
[2] A. Guyot, B. Hochet, and J.-M. Muller, “A way to build efficient carryskip adders,” IEEE Trans. Comput., vol. C-36, no. 10, pp. 1144–1152, Oct. 1987.
[3] M. Alioto and G. Palumbo, “A simple strategy for optimized design of one-level carry-skip adders,” IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 50, no. 1, pp. 141–148, Jan. 2003.
[4] C.-H. Chang, J. Gu, and M. Zhang, “A review of 0.18 μm full adder performances for tree structured arithmetic circuits,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 13, no. 6, pp. 686–695, Jun. 2005.
[5] V. Kantabutra, “Designing optimum one-level carry-skip adders,” IEEE Trans. Comput., vol. 42, no. 6, pp. 759–764, Jun. 1993.
[6] S. Jain et al., “A 280 mV-to-1.2 V wide-operating-range IA- 32 processor in 32 nm CMOS,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers (ISSCC), Feb. 2012, pp. 66–68.