Power Optimization Techniques for High Speed Processor Core in Sub 14nm Technology Node

International Journal of VLSI & Signal Processing

© 2017 by SSRG - IJVSP Journal

Volume 4 Issue 2

Year of Publication : 2017

Authors : Kolusu Siva Mounica and Prashant K. Shah

10.14445/23942584/IJVSP-V4I3P103

How to Cite?

Kolusu Siva Mounica and Prashant K. Shah, "Power Optimization Techniques for High Speed Processor Core in Sub 14nm Technology Node," SSRG International Journal of VLSI & Signal Processing, vol. 4,  no. 2, pp. 11-15, 2017. Crossref, https://doi.org/10.14445/23942584/IJVSP-V4I3P103

Abstract:

Optimization of power can be done at different levels of abstraction e.g., system level, RTL level, Circuit level, Layout level. With continuous scaling of the technology node optimization of power and overall power management on SoC are the key challenges in addition to meeting the performance requirements. This paper gives an idea of various techniques at circuit level to reduce power consumption without affecting the performance of the chip.

Keywords:

 Scaling, Technology node, SoC (Silicon on Chip), Layout.

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