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A 4-bit High Speed, Low Power Flash ADC by Employing Binary Search Algorithm

International Journal of VLSI & Signal Processing
© 2017 by SSRG - IJVSP Journal
Volume 4 Issue 2
Year of Publication : 2017
Authors : Brahmaiah Throvagunta and Prashant K Shah
10.14445/23942584/IJVSP-V4I3P104
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How to Cite?

Brahmaiah Throvagunta and Prashant K Shah, "A 4-bit High Speed, Low Power Flash ADC by Employing Binary Search Algorithm," SSRG International Journal of VLSI & Signal Processing, vol. 4,  no. 2, pp. 16-21, 2017. Crossref, https://doi.org/10.14445/23942584/IJVSP-V4I3P104

Abstract:

 In this paper an analog to digital converter architecture is proposed. The proposed design is based on a mixed approach of flash type ADC combining with Successive Approximation Register type ADC. This new design gives lesser number of comparators compared to conventional flash ADC architecture and so, less power consumption with much low circuit complexity. For a 4-bit design it takes 7 comparators and if you go one bit higher you need two more comparators with some extra digital logic and so on. Based on this design, a 4-bit ADC is done and simulated in Cadence virtuoso Tool using 14nm CMOS technology with power supply voltage of 1.0V. The Proposed ADC consumes 242uW of power and the measured INL and DNL are 0.35 LSB and 0.38 LSB respectively.

Keywords:

Analog to Digital Converter (ADC), Comparator, Flash, DNL, INL, SFDR, SNDR.

References:

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