Energy Consumption of Array-Based Logic Gates

International Journal of VLSI & Signal Processing

© 2017 by SSRG - IJVSP Journal

Volume 4 Issue 3

Year of Publication : 2017

Authors : faraz Ahmed, Zaki Masood and Faiza Sabir

10.14445/23942584/IJVSP-V4I5P101

How to Cite?

faraz Ahmed, Zaki Masood and Faiza Sabir, "Energy Consumption of Array-Based Logic Gates," SSRG International Journal of VLSI & Signal Processing, vol. 4,  no. 3, pp. 1-5, 2017. Crossref, https://doi.org/10.14445/23942584/IJVSP-V4I5P101

Abstract:

Array based transistor stacking has been shown to be an effective technique for improving the power and delay of digital circuits operating in the subthreshold to above nominal voltage range which eventually gives an advantage in overall power-delay-product (PDP) and it comes at the cost of power consumption and area. However, our observation shows that using array based approach, nor all logic cells neither every technology gives an improvement in energy consumption. In this paper, we present our observations to identify whether using array based transistors is beneficial (or not) in comparison with conventional approach in 150 nm technology. The results of incorporating the array-based methodology in standard logic gates such as INV, NOR3 and NAND3, using 150 nm technology, shows that there is not as such improvement by using array-based approach in term of Energy consumption (PDP).

Keywords:

CMOS, Subthreshold region, Low power, power-delay-product (PDP), Transistor sizing.

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