Control Allowance of RISC manner Spending Clock Gating Method

International Journal of VLSI & Signal Processing

© 2017 by SSRG - IJVSP Journal

Volume 4 Issue 3

Year of Publication : 2017

Authors : G.Jefryferrol and S.Maria Toshak

10.14445/23942584/IJVSP-V4I5P103

How to Cite?

G.Jefryferrol and S.Maria Toshak, "Control Allowance of RISC manner Spending Clock Gating Method," SSRG International Journal of VLSI & Signal Processing, vol. 4,  no. 3, pp. 11-15, 2017. Crossref, https://doi.org/10.14445/23942584/IJVSP-V4I5P103

Abstract:

Control has become an significantfeature in the enterprise of broad-spectrum determinationmainframes. The conservative these processors consume too much control as associated with other workplaces. This decrease in these processors is done in the manufacture step itself. But this is a compositeprocedure. If we can appliance the methods for power decrease in obverse end procedure then we can effortlessly design the low controlmainframes without any difficulty. In this paper we are suggesting low power enterprise in front end procedure. There is lot of methods to decrease the power. Low regulator feasting helps to decrease the heat dissipation, increasecordless life and upsurge device dependability. This technique is intended using pipelined structure; complete this can strengthening the speed of the procedure. In this we are using 5-stage pipelining. Determined the approachdevelopment we comprisenumerous low power performances in architectural level also. The highest power reducingtechnique that has been explored in this development is clock gating. Clock Gating is a well-known method to decrease the power ingesting in this plannedSubmission Explicit Processor.

Keywords:

Low power, RISC Processor, Clock gating, Pipelining.

References:

[1] Gated Clock Routing for Low-Power Microprocessor Design, Jaewon Oh and MassoudPedram, Senior Member, IEEE. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 20, NO. 6, JUNE 2001.
[2] LANG, T., MUSOLL, F, and CORTADELLA, J.: „Individual flip-flops with gated clocks for low power datapaths‟, IEEE Trans. Circuits S y ~ tI.I, 1997, 44, (6), pp. 507 516.
[3] Xiaotao Chang, Mingming Zhang, Ge Zhang, Zhimni Zhang and Jim Wang,“Adaptive Clock Gating Technique for Low Power IP Core in SoCDesign”,IEEE International Symposiumon Circuits And Systems,May(2007),pp. 2120 – 2123, 2007.
[4] IBM, Multiprocessor Interrupt controller Data Book, March, 2006.
[5] Kamaraju.M, Lal Kishore.K, Tilak.A.V.N “A Novel Implementation ofApplication specific Instruction – set processor (ASIP) using verilog” Waste Issue 59,Nov 2011.
[6] Jin Soo Kim Sunwoo, Myung H. Sunwoo, “Three low power ASIP processor designs for communications, video, and audio applications”, International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2007. DTIS, pp. 241-244.
[7] Y. Takahashi, T. Sekine, and M. Yokoyama, VLSI implementation of a 4_4-bit multiplier in a two phase drive adiabatic dynamic CMOS logic. , IEICE Trans. Electron., vol. E90-C, no. 10, Oct. 2007, in press.
[8] Qiao Ying-xu, Design of Wireless Sensor Networks Node Based OnTinyOS Operating System.The 3th International Conference on Computer Science and Education[C] 2008.7 1201-1204.
[9] Jilin Li,"Status and Development Trend of Coal M i n e Safety Monitoring System", Journal, Coal Technology, Harbin, 2008(l1), pp. 4- 5.
[10] Wei Chipni, Li Ahaolin, Zheng Qingwei,YeJianfei, and Li Shenglong, “Design of a configurable multichannel interrupt controller”, Second Pacific-Asia Conference on Circuits, Communications and System, vol. 1,Aug 2010, pp. 327–330.
[11] PizhouYe,andChaodong Ling, “A RISC CPU IP core”,Second International Conference on Anticounterfeiting, Security and Identification ,August(2008), pp. 356–359,2008.
[12] H. Jacobson,P. Bose, ZhigangHu,A. Buyuktosunoglu, V.Zyuban,R. Eickemeyer,L. Eisen,J. Griswell,D. Logan,BalaramSinharoy, and J. Tendler,“ Stretching the limits of clock-gating efficiency in server-class processors”,Eleventh International Symposium on Highperformance Computer Architecture,Feburary (2005), pp . 238- 242, 2005.
[13] Xiaotao Chang, Mingming Zhang, Ge Zhang, Zhimni Zhang and Jim Wang,“Adaptive Clock Gating Technique for Low Power IP Core in SoCDesign”,IEEE International Symposium on Circuits And Systems,May(2007),pp. 2120 – 2123, 2007..
[14]S. Ghosh, D. Mohapatra, G. Karakonstantis and K. Roy,“ Voltage Scalable High-speed Robust Hybrid Arithmetic Units Using Adaptive Clocking”IEEE Transactions on Very Large Scale Integration Systems,September(2010),Vol. 18, pp.1301- 1309,2010.
[15] Hai Li, S. Bhunia,Y. Chen,T.N. Vijaykumar and K.Roy,“ Deterministic clock gating for microprocessor power reduction”, Ninth International Symposium on High- Performance Computer Architecture, February (2003), pp. 113 – 122, 2003.