D flip flops for Linear Response Shift Register in CMOS technology

International Journal of VLSI & Signal Processing

© 2017 by SSRG - IJVSP Journal

Volume 4 Issue 3

Year of Publication : 2017

Authors : J.Hinay shelly and B.Craige Shreen

10.14445/23942584/IJVSP-V4I5P104

How to Cite?

J.Hinay shelly and B.Craige Shreen, "D flip flops for Linear Response Shift Register in CMOS technology," SSRG International Journal of VLSI & Signal Processing, vol. 4,  no. 3, pp. 16-20, 2017. Crossref, https://doi.org/10.14445/23942584/IJVSP-V4I5P104

Abstract:

 The incorporated chip manufacturing technology has completed an assessment by decrease the size of a chip and improving its better performance. Reduction of chip announces harms comprising heat degeneracy and power depletion. As chip manufacturing technology is abruptly on the inception of most importantestimation, which contracts chip in dimension and performance, Linear Feedback Shift Register is executed in design level which advances the low power consumption chip, using current CMOS, submicrometer designimplements. Hencethis counter can be aninnovative pacesetter in cryptography and is also valuable to the variability of other applications. Dualisticnumber system using LFSR is offered to decrease these complications. The proposed system strategy gives low power design, by qualifiedexploration of a number of LFSR planning in expressions of hardware application, CMOS design and power consumption.

Keywords:

Linear Feedback Shift Register, Binary numeral system, dynamic logic.

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