An inventive procedure for Composite Organization on Chip confirmation

International Journal of VLSI & Signal Processing

© 2018 by SSRG - IJVSP Journal

Volume 5 Issue 1

Year of Publication : 2018

Authors : Chang chun and Daquan da

10.14445/23942584/IJVSP-V5I1P103

How to Cite?

Chang chun and Daquan da, "An inventive procedure for Composite Organization on Chip confirmation," SSRG International Journal of VLSI & Signal Processing, vol. 5,  no. 1, pp. 10-14, 2018. Crossref, https://doi.org/10.14445/23942584/IJVSP-V5I1P103

Abstract:

Verification is the greatest considerable task in achieving advanced SOC strategies in market. The important competition to be described in the Semiconductor manufacturing is the developing difficulty of SOCs. Manufacturing specialists anticipate that the verification power is almost 70% to 75% of the overall purpose asset. Verification semantic cannot unassisted growth confirmation effectiveness but it must be supplemented by a system to permit repossess to the dangerous level under dissimilar approach IP structures. The expansion in the hardware field made it conceivable the grouping of a widespread yet composite system on a one chip. A task facing the SoC inventors is to agree which system level language we have to practice and how the confirmation mission will be realized.

Keywords:

This Innovative recyclable test bench improvement will reduce the time to market for a chip.

References:

[1] P. Alexander and D. Barton, “A Tutorial Introduction to Rosetta,” Hardware Description Languages Conference (HDLCon'01), San Jose, CA., March 2001.
[2] A Low-Cost and High-Performance Embedded System Architecture and an Evaluation Methodology’’, 2014 IEEE Computer Society Annual Symposium on VLSI.
[3] P. Alexander, R. Kamath and D. Barton, “System Specification in Rosetta”, presented at the IEEE Engineering of Computer Based Systems Symposium, Nashville, Edinburgh, UK, April 2000.
[4] Early development of UVM Based verification environment of image signal processing design using TLM reference model of RTL” an international journal of advanced computer science and Applications vol. 5,No2,2014.
[5] R. Armoni, L. Fix, A. Flaisher, R. Gerth, B. Ginsburg, T. Kanza, A. Landver, S. Mador-Haim, E. Singer man, A. Tiemeyer, M.Y. Vardi, and Y. Zbar, “The For Spec temporal logic: A new temporal property-specification language”, Tools and Algorithms for the Construction and Analysis of Systems (TACAS’02), LNCS, Springer-Verlag, 2002.
[6] P. Bellows and B. Hutchings, “JHDL - An HDL for Reconfigurable Systems”, IEEE Symposium on FPGAs for Custom Computing Machines, IEEE Computer Society Pres",Los Alamitos, CA, pp. 175-184, 1998.
[7] R. Domer, D. D. Gajski, A. Gerstlauer, S. Zhao and J. Zhu, “SpecC: Specification Language and Methodology”, Kluwer Academic Publishers, 2000.
[8] P. L. Flake and Simon J. Davidmann, “Super Log, a unified design language for system-on-chip”, Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 583 -586, 2000.
[9] A. Ghosh, J. Kunkel and S. Liao, “Hardware Synthesis from C/C++”, Design, Automation and Test in Europe, pp.382-383, March 99.
[10] A.A. Jerraya, M. Romdhani, Ph. Le Marrec, F. Hessel, P. Coste, C. Valderrama, G. F. Marchioro, J.M. Daveau,and N.-E. Zergainoh, “Multi-language Specification for System Design and Code sign”, System Level Synthesis, Kluwer Academic Publishers, 1999.
[11] M. Mohtashemi and Azita Mofidian, “Verification Intellectual Property (IP) Modeling Architecture”, Guide to Structured Development Using OpenVera, 2002.
[12] S. Swan, “An Introduction to System Level Modeling in SystemC 2.0. Open System C Initiative (OSCI)”, Cadence Design Systems, Inc. May 2001.
[13] J. Yuan, K. Schultz, C. Pixley, H. Miller, and A. Aziz, “Automatic Vector Generation Using Constraints and Biasing”, Journal of Electronic Testing: Theory and Applications, pp. 107-120, 2000.
[14] R. Otten, P. Stravers, “Challenges in Physical Chip Design”, International Conference on Computer Aided Design (ICCAD), pp. 84-91, 2000.
[15] D. Moundanos, J. A. Abraham, and Y. V. Hoskote “Abstraction techniques for validation coverage analysis and test generation”, IEEE Trans. Computers, vol. 47, no. 1, pp. 2-14, January 1998.