Increasing Fault Coverage in Benchmark Circuit using Design for Testability and Test Pattern Generation using 6NCA
| International Journal of VLSI & Signal Processing |
| © 2018 by SSRG - IJVSP Journal |
| Volume 5 Issue 3 |
| Year of Publication : 2018 |
| Authors : Shashank Srivastava and Tanusree Kaibartta |
10.14445/23942584/IJVSP-V5I3P101
How to Cite?
Shashank Srivastava and Tanusree Kaibartta, "Increasing Fault Coverage in Benchmark Circuit using Design for Testability and Test Pattern Generation using 6NCA," SSRG International Journal of VLSI & Signal Processing, vol. 5, no. 3, pp. 1-10, 2018. Crossref, https://doi.org/10.14445/23942584/IJVSP-V5I3P101
Abstract:
There is high overhead in testing of full scan chain based sequential circuit. Partial scan chain can be used in testing because it involves less overhead. In this paper we propose clustering method to find center of gravity for undetected faults ,this is achieved by placing test point in fan in cone region where we have large number of undetected faults clustered in fan in cone region.we have used 6 Neighborhood cellular automata for generating patterns.we used Hope Tool for circuit Testing.
Keywords:
Cellular Automata(CA),Test Pattern Generation(TPG),Design For Testability(DFT)
References:
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