Design a Low Power Double Tail Comparator using Gated Clock and Power Gating Techniques

International Journal of VLSI & Signal Processing

© 2015 by SSRG - IJVSP Journal

Volume 2 Issue 1

Year of Publication : 2015

Authors : T.Loganayaki and R.Ramya

10.14445/23942584/IJVSP-V2I1P101

How to Cite?

T.Loganayaki and R.Ramya, "Design a Low Power Double Tail Comparator using Gated Clock and Power Gating Techniques," SSRG International Journal of VLSI & Signal Processing, vol. 2,  no. 1, pp. 1-4, 2015. Crossref, https://doi.org/10.14445/23942584/IJVSP-V2I1P101

Abstract:

Comparators are the basic elements for designing the modern analog and mixed signal systems. The speed and area is main factors for high speed applications. Various types of dynamic double tail comparators are compared in terms of Delay, Area, Power, Glitches, Speed and average time. The accuracy of comparators it mainly defined by its power consumption and speed. The comparators are mainly achieving the overall higher performance of ADC. The High speed comparators suffer from low voltage supply. Threshold voltage of the device is not scaled at the same time, as the supply voltage of the device. In modern CMOS technology the double tail comparator is designed by a using the dynamic method, it mainly reduces the power and voltage. The analytical expression method it can obtain an intuition about the contributors, comparator delay and explore the trade-off dynamic comparator design

Keywords:

Double Tail comparator, ADC, Dynamic comparator, Glitches

References:

[1] B. Goll and H. Zimmermann, “A comparator with reduced delay time in 65-nm CMOS for supply voltages down to 0.65,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 56, no. 11, pp. 810–814, Nov. 2009.
[2] S. U. Ay, “A sub-1 volt 10-bit supply boosted SAR ADC design in standard CMOS,” Int. J. Analog Integr. Circuits Signal Process., vol. 66, no. 2, pp. 213–221, Feb. 2011.
[3] A. Mesgarani, M. N. Alam, F. Z. Nelson, and S. U. Ay, “Supply boosting technique for designing very low-voltage mixed-signal circuits in standard CMOS,” in Proc. IEEE Int. Midwest Symp. Circuits Syst. Dig. Tech. Papers, Aug. 2010, pp. 893–896.
[4] B. J. Blalock, “Body-driving as a Low-Voltage Analog Design Technique for CMOS technology,” in Proc. IEEE Southwest Symp. Mixed-Signal Design, Feb. 2000, pp. 113–118.
[5] M. Maymandi-Nejad and M. Sachdev, “1-bit quantiser with rail to rail input range for sub-1V modulators,” IEEE Electron. Lett., vol. 39, no. 12, pp. 894–895, Jan. 2003.
[6] Y. Okaniwa, H. Tamura, M. Kibune, D. Yamazaki, T.-S. Cheung, J. Ogawa, N. Tzartzanis, W. W. Walker, and T. Kuroda, “A 40Gb/ s CMOS clocked comparator with bandwidth modulation technique,” IEEE J. Solid-State Circuits, vol. 40, no. 8, pp. 1680–1687, Aug. 2005.
[7] B. Goll and H. Zimmermann, “A 0.12 μm CMOS comparator requiring 0.5V at 600MHz and 1.5V at 6 GHz,” in Proc. IEEE Int. Solid-State Circuits Conf., Dig. Tech. Papers, Feb. 2007, pp. 316–317.
[8] B. Goll and H. Zimmermann, “A 65nm CMOS comparator with modified latch to achieve 7GHz/1.3mW at 1.2V and 700MHz/47μW at 0.6V,” in Proc. IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2009, pp. 328–329.
[9] B. Goll and H. Zimmermann, “Low-power 600MHz comparator for 0.5 V supply voltage in 0.12 μm CMOS,” IEEE Electron. Lett., vol. 43, no. 7, pp. 388–390, Mar. 2007.
[10] D. Shinkel, E. Mensink, E. Klumperink, E. van Tuijl, and B. Nauta, “A double-tail latch-type voltage sense amplifier with 18ps Setup+Hold time,” in Proc. IEEE Int. Solid-State Circuits Conf., Dig. Tech. Papers, Feb. 2007, pp. 314–315.
[11] P. Nuzzo, F. D. Bernardinis, P. Terreni, and G. Van der Plas, “Noise analysis of regenerative comparators for reconfigurable ADC architectures,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 55, no. 6, pp. 1441–1454, Jul. 2008.
[12] A. Nikoozadeh and B. Murmann, “An analysis of latched comparator offset due to load capacitor mismatch,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 53, no. 12, pp. 1398–1402, Dec. 2006.
[13] S. Babayan- Mashhadi and R. Lotfi, “An offset cancellation technique for comparators using body-voltage trimming,” Int. J. Analog Integr. Circuits Signal Process., vol. 73, no. 3, pp. 673–682, Dec. 2012.
[14] J. He, S. Zhan, D. Chen, and R. J. Geiger, “Analyses of static and dynamic random offset voltages in dynamic comparators,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 56, no. 5, pp. 911–919, May 2009.