Improved Latch Type Modified Sense Amplifier for Suppress Coupling

International Journal of VLSI & Signal Processing

© 2019 by SSRG - IJVSP Journal

Volume 6 Issue 2

Year of Publication : 2019

Authors : Kriti Telang , Mr. Dinesh Chand Gupta

10.14445/23942584/IJVSP-V6I2P101

How to Cite?

Kriti Telang , Mr. Dinesh Chand Gupta, "Improved Latch Type Modified Sense Amplifier for Suppress Coupling," SSRG International Journal of VLSI & Signal Processing, vol. 6,  no. 2, pp. 1-4, 2019. Crossref, https://doi.org/10.14445/23942584/IJVSP-V6I2P101

Abstract:

At the point when constantly increment the semiconductor manufacturing technology, at that point Continuous turn away the channel length and area of the CMOS with the forceful procedure variety and signal coupling impact. Here clarified how the activities of sense amplifier bother by the property of coupling impact. In this dissertation we structure the single stage amplifier, altered single stage amplifier and multistage amplifier. The operational amplifier contains the high addition, high input impedance and low output impedance.

Keywords:

Operational Amplifier (OP-AMP), CMOS, Metal oxide semiconductor (MOS), SRAM.

References:

[1] Bijan Davari, “CMOS Technology: Present and Future”, Semiconductor and Research Development Center (SRDC).
[2] Chao Zhao and Jinjuan Xiang, “Atomic Layer Deposition (ALD) of Metal Gates for CMOS”appliedsciences.
[3] https://www.britannica.com/technology/complementary-metal-oxide-semiconductor
[4] Sridhar Abburi and Rapoul Anil Kumar, “Design Methodologies and Strategies for Low Power VLSI” International Journal for Modern Trends in Science and Technology Volume: 03, Issue No: 06, June 2017.
[5] Sparsh Mittal and Rujia Wang, “DESTINY: A Comprehensive Tool with 3D and Multi-Level Cell Memory Modeling Capability”, Journal of. Low Power Electron. Appl. 2017, 7, 23.
[6] Ham Hamsa and Thangadurai Natarajan, “A
[7] Study of Semiconductor Memory Technology by Comparing Volatile and NonVolatile Memories”, Journal of Advanced Research in Dynamical and Control Systems · July 2018.
[8] A.P.Dhande1 , Satish S, “Vlsi Implementation Of Ternary Gates Using Tanner Tool”, 2nd International Conference on Devices, Circuits and Systems (ICDCS), 2014
[9] P.K.Dhivya , Gayathri and P. Harini , “Design of Low Power 1 Bit Full Adder Using Variable Sub- Threshold Voltage at 45 Nm Technology”, International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering, Vol. 6, Issue 3, March 2017.