Optimized Tsv Based 3d Integrated Circuit For Improve Power With Reduced Area Of Circuit

International Journal of VLSI & Signal Processing

© 2019 by SSRG - IJVSP Journal

Volume 6 Issue 3

Year of Publication : 2019

Authors : Aditya Sharma, Mr. Dinesh Chand Gupta

10.14445/23942584/IJVSP-V6I3P101

How to Cite?

Aditya Sharma, Mr. Dinesh Chand Gupta, "Optimized Tsv Based 3d Integrated Circuit For Improve Power With Reduced Area Of Circuit," SSRG International Journal of VLSI & Signal Processing, vol. 6,  no. 3, pp. 1-5, 2019. Crossref, https://doi.org/10.14445/23942584/IJVSP-V6I3P101

Abstract:

The impact of huge coupling capacitance between TSVs on the extension, power and coupling confusion in 3D interconnects likewise offers genuine difficulties to the presentation of 3D-IC. Because of the level of design multifaceted nature presented by TSVs in 3D ICs, the significance of beginning time assessment and streamlining of extension, power and sign respectability of 3D circuits can't be disregarded. The interesting commitment of this work is to create strategies for exact examination of timing, power and coupling noise over different stacked gadget layers during the floor arranging stage. Fusing the effect of TSV and the stacking of various gadget layers inside floor arranging structure will accomplish 3D designs with predominant execution.

Keywords:

3D ICs, Silicon Integrated Circuits, Through Silicon Vias.

References:

[1] S. Borkar, "3D integration for energy efficient system design," in Proc. Of ACM/IEEE Design Automation Conf., 2011.
[2] K. Banerjee, S. Souri, P. Kapur, and K. C. Saraswat, “3-D ICS: A novel chip design for improving deep-sub micrometer interconnect performance and system-on-chip integration,” Proc. IEEE, vol. 89, no. 5, pp. 602–633, May 2001.
[3] International Technology Roadmap for Semiconductors, “Semiconductor Industry Association,” 2015. Available: http://www.itrs2.net
[4] S. Das, A. Chandrakasan, and R. Reif, “Three-dimensional integration: Performance, design methodology, and CAD tools,” in Proc. of IEEE Symposium on VLSI, pp. 13– 18 Feb. 2003.
[5] J. Yang, K. Athikulwongse, Y. Lee, S. Lim, D. Pan, “TSV stress aware timing analysis with applications to 3D-IC layout optimization”, Proc. of the 47th ACM/IEEE Design Automation Conf., June 13-18, 2010.
[6] M. Jung, J. Mitra, D. Pan, S. Lim, “TSV stress-aware full-chip mechanical reliability analysis and optimization for 3D IC”, Communications of the ACM, vol.57 no.1, January 2014
[7] B. Shi, A. Srivastava, A. Bar-Cohen, “Hybrid 3D-IC Cooling Systems Using Microfluidic Cooling and Thermal TSVs”, IEEE Computer Society Annual Symposium on VLSI, 2012.
[8] Intel Technology Journal, “Intel’s 45nm CMOS Technology”, vol. 12, no. 02, June 17, 2008.
[9] D.H. Kim, S. Mukhopadhyay, and S. K. Lim. "TSV-aware interconnect distribution models for prediction of delay and power consumption of 3-d stacked ICs," Computer-Aided Design of Integrated Circuits and Systems, IEEE Trans. on 33.9 (2014): 1384-1395