Modified radix 12 Multiplier for reducing area of designed circuit with reduce time delay

International Journal of VLSI & Signal Processing

© 2019 by SSRG - IJVSP Journal

Volume 6 Issue 3

Year of Publication : 2019

Authors : Akshay Sharma, Mr. Dinesh Chand Gupta

10.14445/23942584/IJVSP-V6I3P102

How to Cite?

Akshay Sharma, Mr. Dinesh Chand Gupta, "Modified radix 12 Multiplier for reducing area of designed circuit with reduce time delay," SSRG International Journal of VLSI & Signal Processing, vol. 6,  no. 3, pp. 6-9, 2019. Crossref, https://doi.org/10.14445/23942584/IJVSP-V6I3P102

Abstract:

A multiplier utilizing the radix-4 (or adjusted Booth) calculation is exceptionally effective because of the simplicity of incomplete item age, though the radix-8 Booth multiplier is delayed because of the unpredictability of producing the odd products of the multiplicand. In this paper, this issue is eased by the utilization of estimated structures. A surmised 2-bit snake is purposely intended for figuring the total of 1 and 2 of a double number. This snake requires a little territory, a low power and minimum delay. In this manner, the 2-bit snake is utilized to actualize the less critical segment of a recoding adder for creating the triple multiplicand with no conveys spread. In the quest for an exchange off among exactness and power utilization, two marked 12 * 12 bit rough radix-8 Booth multipliers are planned utilizing the surmised recoding snake with and without the truncation of various less critical bits in the halfway items. The proposed surmised multipliers are quicker and more power productive than the precise Booth multiplier. The multiplier with 15-bit truncation accomplishes the best by and large execution regarding equipment and precision when contrasted with other estimated Booth multiplier structures.

Keywords:

half adder, full adder, multiplier, multiplier, 8*8 radix multiplier, 16*16 radix multiplier.

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