A Review on Low Power Memory Design Technique

International Journal of VLSI & Signal Processing

© 2019 by SSRG - IJVSP Journal

Volume 6 Issue 3

Year of Publication : 2019

Authors : Bhumika Chaurasia, Nishi Pandey, Meha Shrivastava

10.14445/23942584/IJVSP-V6I3P103

How to Cite?

Bhumika Chaurasia, Nishi Pandey, Meha Shrivastava, "A Review on Low Power Memory Design Technique," SSRG International Journal of VLSI & Signal Processing, vol. 6,  no. 3, pp. 10-13, 2019. Crossref, https://doi.org/10.14445/23942584/IJVSP-V6I3P103

Abstract:

This article describes the 10L Ultra Low Power Static RAM (ULP) for Internet Object (IoT) applications running below the threshold. The proposed SRAM, as a rule, operate at low supply voltage with a high static and dynamic noise margin. IoT applications require a battery compatible low leakage memory architecture in the lower threshold region. Therefore, to improve leakage energy consumption and cell stability, this technical document presents the reliable SRAM 10T power system. The proposed cell uses a p-MOS transistor with a power system to reduce power leakage or static power in standby mode. Also, due to the overlapping of the n-MOS transistor in the 10T SRAM latch and the separation of the read path of the
10T SRAM latch, static and dynamic noise reserves in reading and write operations show significant tolerance. There are variations in the process
parameters, voltage and temperature (PVT) of the device. The proposed SRAM significantly improves leakage power, static noise reading (RSNM), static noise recording (WSNM), write capacity or write trigger point (WTP), read-write power and dynamic read field (DRM) show performance. Also, these parameters of the proposed cell are observed in 8 kilobits (KB) of SRAM and are compared with the existing SRAM architecture. Based on the Monte Carlo simulation results, it was found that the leakage power of the proposed low SRAM LVT 10T threshold is decreasing.

Keywords:

Memory design; Ultra power; Circuit design

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