A Review on ASIC Flow Employing EDA Tools by Synopsys

International Journal of VLSI & Signal Processing

© 2020 by SSRG - IJVSP Journal

Volume 7 Issue 1

Year of Publication : 2020

Authors : Neha Deshpande, Sowmya K B

10.14445/23942584/IJVSP-V7I1P104

How to Cite?

Neha Deshpande, Sowmya K B, "A Review on ASIC Flow Employing EDA Tools by Synopsys," SSRG International Journal of VLSI & Signal Processing, vol. 7,  no. 1, pp. 15-19, 2020. Crossref, https://doi.org/10.14445/23942584/IJVSP-V7I1P104

Abstract:

The development in automation tools and their algorithms has made it convenient to design ASIC processors and perform extensive analysis of their parameters. Application Specific Integrated Circuit (ASIC) design flow provides the flexibility of modeling the blocks as hardware accelerator which can be made a part of the chip. In ASIC flow there are various processes like logic or physical synthesis, static timing analysis, formal verification, design for testability which provides details about area, power, timing information, violating paths that required for designing the block to so that it can be integrated into the chip along with other blocks. In regard to this, the paper provides an insight to the brief literature survey of the proposed works, their functioning with respect to Synopsys’s EDA tools and the dependency between these tools. Thus, the methods used in the flow are designed such that the critical parameters of the design like power, area and timing can be optimized to a great extent with the aid of EDA tools.

Keywords:

Application Specific Integrated Circuit, Register Transfer Logic, Electronic Design Automation, Design Compiler, Prime Time, IC Compiler, Synthesis, Timing Analysis, Floor planning, Optimization, Power, Area.

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