Design of A Low Power 16- Bit CSLA Using Binary To Excess-1 Converter

International Journal of VLSI & Signal Processing

© 2020 by SSRG - IJVSP Journal

Volume 7 Issue 2

Year of Publication : 2020

Authors : Anjali Raman,Chirukoti Anusha,C.Sucharitha, Shaik Mohammed Rafi,Dr.SK.Fairooz

10.14445/23942584/IJVSP-V7I2P103

How to Cite?

Anjali Raman,Chirukoti Anusha,C.Sucharitha, Shaik Mohammed Rafi,Dr.SK.Fairooz, "Design of A Low Power 16- Bit CSLA Using Binary To Excess-1 Converter," SSRG International Journal of VLSI & Signal Processing, vol. 7,  no. 2, pp. 11-13, 2020. Crossref, https://doi.org/10.14445/23942584/IJVSP-V7I2P103

Abstract:

For math functions , the fastest adders used is Carry Select Adder ( CSLA) in many data processors. CSLA is an Application Specific Integrated Circuit (ASIC) developed by modifying the CSLA Regular Square Root Structure (SQRT). The main goal is a poster design that has less space and strength compared to the regular CSLA SQRT to assess the proposed design performance in terms of area and power with logical voltage and custom design. However, CSLA is not effective in the region because it uses multiple pairs of corrugation load additives (RCA) to generate a partial amount and a conversion taking into account the input entry then the final sum and the conversion specified by the multiplexers. The basic idea of this synthesis is to use BEC as an alternative of a RCA with a regular CSLA to achieve lower power and region consumption. Despite the delay, CSLA is more beneficial in that it requires low power and area consumption. The proposed design was developed using Verilog-HDL and compiled into XILINX ISE 14.7 Software Tool.

Keywords:

Binary to Excess-1 Converters (BEC), Carry Select Adder (CSLA), squareroot (SQRT) CSLA architecture, Low power, Ripple Carry Adder(RCA).

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