Application of DFT on UART Implmenatation

International Journal of VLSI & Signal Processing

© 2020 by SSRG - IJVSP Journal

Volume 7 Issue 2

Year of Publication : 2020

Authors : Madhura R, Sharanbsav A, Vaibhav Krishnan, A.G Sai Tejas, Akshita Deep

10.14445/23942584/IJVSP-V7I2P104

How to Cite?

Madhura R, Sharanbsav A, Vaibhav Krishnan, A.G Sai Tejas, Akshita Deep, "Application of DFT on UART Implmenatation," SSRG International Journal of VLSI & Signal Processing, vol. 7,  no. 2, pp. 14-28, 2020. Crossref, https://doi.org/10.14445/23942584/IJVSP-V7I2P104

Abstract:

Asynchronous serial communication is sometimes enforced by Universal Asynchronous Receiver Transmitter (UART), largely used for brief distance, low speed, low value information exchange between processor and peripherals. UART permits full duplex serial communication link, and is employed in electronic communication and system. there's a desire for realizing the UART perform a single chip. Further, style systems not full testability is hospitable the exaggerated chance of product failures and incomprehensible market opportunities. Also, there's a desire to confirm the info transfer is error proof. This targets the introduction of intrinsic self-take a look at (BIST) and standing register to UART, to beat the on top of 2 constraints of testability and information integrity. The 8-bit UART with standing register and BIST module is coded in Verilog HDL and synthesized and simulated using Vivado Hlx design edition and van be realized on FPGA if required. The results indicate that this model eliminates the requirement for higher finish, pricey testers and thereby it will scale back the event time and price. The expanding development of sub-micron innovation has brought about the trouble of testing. Design and test engineers must choose the option to acknowledge new obligations that had been performed by gatherings of experts in the earlier years. Design engineers who don't plan frameworks in light of full testability open themselves to the expanded chance of item disappointments and botched market chances. BIST is a plan strategy that permits a circuit to test itself. the test execution accomplished with the usage of BIST is demonstrated to be sufficient to balance the disincentive of the equipment overhead delivered by the extra BIST circuit. The procedure can give shorter test time contrasted with a remotely applied test and permits the utilization of minimal effort test gear during all phases of creation

Keywords:

UART, BIST, Error check, Status register, LFSR

References:

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Manuals-
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[2] Vivado Design Suite User Guide “High-Level Synthesis”, Xilinx, UG902 (v2017.1) April 5, 2017
Websites-
[1] https://www.xilinx.com/products/design-tools/vivado.html
[2] https://microcontrollerslab.com/uart-communication-working-applications/