High Performance and Low Power Asynchronous Data Sampling with Power Gated Double Edge Triggered Flip-Flop

International Journal of VLSI & Signal Processing

© 2015 by SSRG - IJVSP Journal

Volume 2 Issue 1

Year of Publication : 2015

Authors : R. Aruna and S.Thenappan

10.14445/23942584/IJVSP-V2I1P103

How to Cite?

R. Aruna and S.Thenappan, "High Performance and Low Power Asynchronous Data Sampling with Power Gated Double Edge Triggered Flip-Flop," SSRG International Journal of VLSI & Signal Processing, vol. 2,  no. 1, pp. 9-12, 2015. Crossref, https://doi.org/10.14445/23942584/IJVSP-V2I1P103

Abstract:

Power consumption and energy efficiency is a major role in sequential circuit design. Power gating is a technique that is used to reduce the static power consumption of idle modules. Usage of Dual Edge Triggered Flip-flop (DETFF) is an efficient technique since it consumes the clock frequency and less power than Double Edge Triggered Flip-flops (DETFF’s). Integrating power gating technique with DETFF reduces the power consumption and leakage power further, but it leads to asynchronous data sampling problem. In this paper, two methods have been used to eradicate the asynchronous data sampling problem and their power analysis has been estimated. In order to reduce the leakage power consumption further, a new design has proposed for a DETFF. Based on his new design, the two methods have been implemented using 130 μm Tanner EDA tool.

Keywords:

Double Edge Trigger Flip Flop, Clock Gating, Power Gating, Single Edge trigger Flip Flop

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