PERFORMANCE COMPARISON BETWEEN ULTRA LOW POWER ALU WITH CMOS AND GDI TECHNIQUES
International Journal of VLSI & Signal Processing |
© 2020 by SSRG - IJVSP Journal |
Volume 7 Issue 2 |
Year of Publication : 2020 |
Authors : Vanajeswari Imandi, Nagalakshmi Harisha A |
How to Cite?
Vanajeswari Imandi, Nagalakshmi Harisha A, "PERFORMANCE COMPARISON BETWEEN ULTRA LOW POWER ALU WITH CMOS AND GDI TECHNIQUES," SSRG International Journal of VLSI & Signal Processing, vol. 7, no. 2, pp. 43-46, 2020. Crossref, https://doi.org/10.14445/23942584/IJVSP-V7I2P107
Abstract:
The ALU is one of the most fundamental operational units in any processor. The ALU can be characterized as the combinational unit, which is utilized to play out its intelligence and number juggling units. This paper presents a low power rapid Arithmetic Logic Unit (ALU) in 14 nm technology utilizing Multi-limit voltage semiconductor logic and Gate Diffusion Input procedure. Its presentation is contrasted and regular CMOS method. The reproduced outcomes uncovered better execution attributes of different number juggling and logic elements of a 1-piece ALU utilizing VTV and GDI procedures contrasted with customary CMOS strategy. This procedure permits diminishing power scattering and deferral while keeping up the low intricacy of logic design.
Keywords:
VTV technique, GDI, ALU, Digital Design.
References:
[1] S. D. Brown, R. J. Francis, J. Rose, and Z. G. Vranesic, “Field Programmable Gate Arrays”. Boston,MA,USA:Kluwer,1992.
[2] S. Seo et al., “Reproducible resistance switching in polycrystalline NiO films,” Appl. Phys. Lett.,vol.85,no.23,pp.5655–5657,2004.
[3] L. Torres, R. M. Brum, L. V. Cargnini, and G. Sassatelli, “Trends on the application of emerging nonvolatile memory to processors and programmable devices,” in Proc. IEEE Int. Symp. Circuits Syst.(ISCAS), May 2013, pp.101–104.
[4] M. Wang et al., “A novel Cux SiyO resistive memory in logic technology with excellent data retention and resistance distribution for embedded applications,” in Proc. Symp. VLSI Technol. (VLSIT),Jun.2010,pp.89–90.
[5] X. Xue et al., “Nonvolatile SRAM cell based on Cux O,” in Proc. 9th Int. Conf. Solid-State Integr.-Circuit Technol. (ICSICT), Oct. 2008, pp. 869–871.
[6] N. Bruchon, L. Torres, G. Sassatelli, and G. Cambon, “Technological hybridization for efficient runtime reconfigurable FPGAs,” in Proc. IEEE Comput. Soc. Annu. Symp. VLSI (ISVLSI), Mar. 2007, pp. 29–34.
[7] Alioto, M., Cataldo, G.D., Palumbo, G.: ‘Mixed full adder topologies for high-performance low-power arithmetic circuits,' Microelectron. J., 2007, 38, (1), pp. 130–139.
[8] Bui, H.T., Wang, A., Jiang, Y.: ‘Design and analysis of low-power 10- transistor full adders using novel XORXNOR gates’, IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., 2002, 49, (1), pp. 25–30.
[9] M.Aruna Devi and A.Jagadeeswaran, "Design of Low Power Sense Amplifier Flip Flop using GDI and FinFET Techniques" SSRG International Journal of Electronics and Communication Engineering 5.5 (2018): 4-10.
[10] Kalicherla Himabindu, Mr. K.Hariharan, "Design of territory and power powerful complete adder in 180nm", the worldwide convention on Networks and Advances in Computational technologies, 20,2017.
[11] H. T. Bui, A. Okay. Al-Sheraidah, and Y.Wang, ―New 4-transistor XOR and XNOR designs,‖ Tech. Rep., Florida Atlantic Univ., Boca Raton, 1999.
[12] Sreehari Veeramachaneni and Hyderabad, ―New stepped forward 1-bit snake cells‖, CCECE/CCGEI, Niagara Falls. Canada can also five-7 2008, pp.
735-738..
[13] Morgenshtein A, Yuzhaninov V, Kovshilovsky A. Fish, Full-swing gate diffusion input logic-case-study of lowpower CLA adder design, Integr. VLSI, J., 2014, 47: 62– 70.