A Novelty of Emergent Technology Challenges of Dielectric Films at14nm Era

International Journal of VLSI & Signal Processing

© 2022 by SSRG - IJVSP Journal

Volume 9 Issue 2

Year of Publication : 2022

Authors : M. L. N. Acharyulu, N. S. Murthi sarma, K. Lal kishore

10.14445/23942584/IJVSP-V9I2P102

How to Cite?

M. L. N. Acharyulu, N. S. Murthi sarma, K. Lal kishore, "A Novelty of Emergent Technology Challenges of Dielectric Films at14nm Era," SSRG International Journal of VLSI & Signal Processing, vol. 9,  no. 2, pp. 5-8, 2022. Crossref, https://doi.org/10.14445/23942584/IJVSP-V9I2P102

Abstract:

This paper deals with the challenges ahead of dielectric film applicable in sub-nanometer technology, which will be varying characteristics with different applied methods. To form finfets in the sub-nanometer era. It gets harder for ordinary Field Effect Transistors to compress short-term channel output as technology advances beyond 14nm. For the coming generation, FinFET technology offers a possible solution to those problems. The sophisticated electrostatic controller provided by the FinFET gate wraps channel without significant doping enables reliable distribution and enhanced performance for the CMOS circuit. FinFET can be implemented using a sizable portion of CMOS-based processes. However, many new applications are still available, and difficulties and techniques must be improved to meet the demanding FinFET specifications.
       This study will describe various novel 14nm FinFET dielectric film techniques and applications, including Atomic Layer Deposition boron and phosphor silicate glass solid-state doping, flowable chemical vapour deposition streaming film Shallow-Trench-Isolation (STI), and interlayer dielectric gap fill(ILD), self-portrait films of nitride (SAC), and others. Additionally, the results of those procedures' initial tests will be discussed. The difficulties with those apps will then be thoroughly explained. The issues will be addressed to meet the practical requirements by taking into account the development processes of those dielectric films utilised in various applications.

Keywords:

FinFET, PTSL, BSG, PSG, SCE, CVD, ILD, SAC, STI, Die-electric.

References:

[1] B. Yu et al., IEDM Tech. Dig., pp. 251, 2002.
[2] Digh Hisamoto et al., T-ED, vol. 57, no. 12, pp. 2320-2325.
[3] S. Natarajan et al., "A 14nm Logic Technology Featuring 2nd-Generation FinFET Air-Gap Interconnects Self-Aligned Double Patterning and a 0.0588 m2 SRAM", pp. 71-73, 2014.
[4] K. Cheng et al., "Bottom oxidation through STI (BOTS)-A Novel Approach to Fabricate Dielectric Isolated FinFETs on Bulk Substrates," VLSI-Technology, 2014.
[5] T. Park et al., Process of Symposium on VLSl Technology Digest of Technical Papers, pp. 135-136, 2003.
[6] K. Okano et al., IEDM, pp. 721-724, 2005.
[7] S. Natarajan et al., IEDM14-73, pp. 3.7.1 - 3.7.3, 2014.
[8] C. Auth, et al., VLSI Tech. 2012, pp. 131-132
[9] H. J. Yoo et al., "Demonstration of a reliable high-performance and yielding Air gap interconnect process," IITC, pp. 1-3, 2012.
[10] Y. Chen, M. Mohamed, M. Jo, U. Ravaioli, R. Xu, "Junctionless MOSFETs with laterally graded-doping channel for analog/RF applications," Journal of comp. electronics, vol. 12, no. 4, pp. 757-764, 2013.
[11] S. E. Liu, J. Wang, Y. Lu, D. Huang, C. F. Huang, W. H. Hsieh, J. H. Lee, Y. S. Tsai, J. R. Shih, Y. -H. Lee and K. Wu, "Self-Heating Effect in FinFETs and Its Impact on Devices Reliability Characterization," in Proc. of the IEEE International Reliability Physics Symposium (IRPS), 2014, pp. 4A.4.1-4A.4.4 [12] H. C. Sagong, K. Choi, J. Kim, T. Jeong, M. Choe, H. Shim, W. Kim, J. Park, S. Shin, and S. Pae, "Modeling of FinFET Self-Heating Effects in Multiple FinFET Technology Generations with Implication for Transistor and Product Reliability," in Symp. VLSI Technol. Dig. Tech. Papers, 2018, pp. T121-T122
[13] H. Jiang, H. C. Sagong, J. Kim, J. Park, S. Shin, and S. Pae, "Localized Layout Effect Related Reliability Approach in 8nm FinFETs Technology: From Transistor to Circuit," in Proc. of the IEEE International Reliability Physics Symposium (IRPS), 2019, pp. 1-5.
[14] K. Choi, H. C. Sagong, W. Kang, H. Kim, J. Hai, M. Lee, B. Kim, S. Lee, H. Shim, J. Park, Y. Cho, H. Rhee, and S. Pae, "Reliability Characterization of 7nm Process Technology featuring EUV," in Symp. VLSI Technol. Dig. Tech. Papers, 2019, pp. T16-T17