A Review on Area Efficient Parallel FIR Digital Filter Implementation

International Journal of VLSI & Signal Processing

© 2015 by SSRG - IJVSP Journal

Volume 2 Issue 1

Year of Publication : 2015

Authors : Arunadevi A . ,Chitra K. , GunaNandhini S. , Raghupathi T. , and Rejusha M

10.14445/23942584/IJVSP-V2I1P104

How to Cite?

Arunadevi A . ,Chitra K. , GunaNandhini S. , Raghupathi T. , and Rejusha M, "A Review on Area Efficient Parallel FIR Digital Filter Implementation," SSRG International Journal of VLSI & Signal Processing, vol. 2,  no. 1, pp. 13-16, 2015. Crossref, https://doi.org/10.14445/23942584/IJVSP-V2I1P104

Abstract:

Digital signal processing (DSP) applications use various types of filters among which, digital parallel FIR filters are very widely used in various applications. Now a day’s implementation of digital FIR filter using DSP technique has several practical difficulties such as high delay and low speed. To overcome these practical difficulties, the parallel FIR digital filters are implemented using multipliers in VLSI. But implementation using multipliers in VLSI increases the hardware cost. So, to provide low power consumption, low area, high speed and low delay, the multipliers are replaced using adders. Exchanging of multipliers with additional adders is more beneficial because adders are less in weigh in terms of silicon area and thus hardware implementation can made simpler.

Keywords:

Digital Signal Processing (DSP), Fast Finite Impulse Response (FIR) Algorithms (FFA), Parallel FIR, Very Large Scale Integration (VLSI).

References:

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