Design and Implementation of RISC-V ISA (RV32IM) on FPGA

International Journal of VLSI & Signal Processing

© 2023 by SSRG - IJVSP Journal

Volume 10 Issue 2

Year of Publication : 2023

Authors : Anmol Singh, Arpit Kumar, Abhishek Singh, R. Anirudh Reddy, K. N. Pushpalatha

10.14445/23942584/IJVSP-V10I2P103

How to Cite?

Anmol Singh, Arpit Kumar, Abhishek Singh, R. Anirudh Reddy, K. N. Pushpalatha, "Design and Implementation of RISC-V ISA (RV32IM) on FPGA," SSRG International Journal of VLSI & Signal Processing, vol. 10,  no. 2, pp. 17-21, 2023. Crossref, https://doi.org/10.14445/23942584/IJVSP-V10I2P103

Abstract:

RISC-V, an open-source Instruction Set Architecture, originated from the collaborative efforts of researchers at the University of California, Berkeley, in 2010. It is a basic Load and Store type architecture based on traditional principles of RISC whilst providing flexibility in terms of extensions to the base Integer Set such as multiply, floating point and atomic instructions. This paper details the Design and Implementation of 5 stages pipelined RV32IM (base integer set with multiply extension). The design also incorporates a 2-bit branch predictor for increased throughput. Analysis and Verification have been performed for proper decoding, pipelined operation, branch prediction, stalling, memory access, and overall functionality. Verilog HDL on Intel QuestaSim has been used to design the core and simulation. DE 10 Lite board with Max 10 family of FPGA has been used for hardware synthesis and analysis of the design.

Keywords:

RISC-V, Instruction Set Architecture, RV32IM, 5-stage pipeline, DE10 Lite FPGA.

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