Call For Paper - Upcoming Conferences
Research Article | Open Access | Download PDF
Volume 13 | Issue 5 | Year 2026 | Article Id. IJEEE-V13I5P116 | DOI : https://doi.org/10.14445/23488379/IJEEE-V13I5P116

Performance Analysis of Energy Efficient Reversible Logic Circuits using Gate Diffusion Input Technique for Low Power Application

Sujata S. Chiwande, Pravin K. Dakhole

Received Revised Accepted Published
24 Feb 2026 23 Mar 2026 22 Apr 2026 30 May 2026

Citation :

Sujata S. Chiwande, Pravin K. Dakhole, "Performance Analysis of Energy Efficient Reversible Logic Circuits using Gate Diffusion Input Technique for Low Power Application," International Journal of Electrical and Electronics Engineering, vol. 13, no. 5, pp. 196-209, 2026. Crossref, https://doi.org/10.14445/23488379/IJEEE-V13I5P116

Abstract

Technologies are developing exponentially in present era and as device become more compact the consumption of power is becoming the major limitation in all devices. A new technique for designing of low power digital circuits is the Gate Diffusion Input (GDI) which retains low logic design complexity. Use of GDI technology in reversible logic drastically improves circuit complexity, power dissipation and area. The main aim of this research is to design and implement the various digital logic circuits using GDI technique for reversible logic circuit. In this research Basic reversible gates like Feynman, Toffoli, Peres gates are implement using GDI technique. Further for design various digital combinational circuits propose new GDI base reversible gates such as RGG, RGG2 and PRGG1. Some trade-offs are made in the design to increase performance efficiency. Propose gate is used to implement a digital circuit such as the Full Adder, 4:1 Multiplexer, Demultiplexer, 4-bit magnitude Comparator, 8:3 Encoder and 4:16 BCD to Decimal Decoder and executes the parametric analysis for these circuits. The propose designs found enormous improvement over power dissipation, area and gate count with the existing design. Comparison is demonstrated in the result section. For implementation and simulation EDA Tanner tool, V13 is used using 90nm technology with supply voltage 1V.

Keywords

Reversible Logic, GDI, Multiplexer, Magnitude comparator, Low power encoder, BCD decoder.

References

  1. R. Landauer, “Irreversibility and Heat Generation in the Computing Processl,” IBM Journal of Research and Development, vol. 5, no. 3, pp. 183-191, 1961.
    [CrossRef] [Google Scholar] [Publisher Link]
  2. C.H. Bennett, “Logical Reversibility of Computation,” IBM Journal of Research and Development, vol. 17, no. 6, pp. 525-532, 1973.
    [CrossRef] [Google Scholar] [Publisher Link]
  3. A. Morgenshtein, A. Fish, and I.A. Wagner, “Gate-Diffusion Input (GDI) A Power-Efficient Method for Digital Combinatorial Circuits,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 10, no. 5, pp. 566-581, 2022.
    [CrossRef] [Google Scholar] [Publisher Link]
  4. Sheba Diamond Thabah, and Prabir Saha, “New Design Approaches of Reversible BCD Encoder using Peres and Feynman Gates,” The Korean Institute of Communications and Information Sciences (KICS) ICT Express, vol. 6, no. 1, pp. 38-42, 2020.
    [CrossRef] [Google Scholar] [Publisher Link]
  5. Himanshu Thapliyal, and A.P Vinod, “Design of Reversible Sequential Elements with Feasibility of Transistor Implementation,” 2007 IEEE International Symposium on Circuits and Systems (ISCAS), New Orleans, LA, USA, pp. 625-628, 2007.
    [CrossRef] [Google Scholar] [Publisher Link]
  6. M. Aditya, Y.B. Nithin Kumar, and M.H. Vasantha, “Reversible Full/Half Adder with Optimum Power Dissipation,” 2016 10th International Conference on Intelligent Systems and Control (ISCO), Coimbatore, India, pp. 1-4, 2016.
    [CrossRef] [Google Scholar] [Publisher Link]
  7. P. Gowthami, and R.V.S. Satyanarayana, “Design of Digital Adder Using Reversible Logic,” Journal of Engineering Research and Applications, vol. 6, no. 2, pp. 53-57, 2016.
    [Google Scholar] [Publisher Link]
  8. Vandana Shukla et al., Chapter 13 - Design of Array Multiplier Circuit using Reversible Logic Approach with Optimized Performance Parameters, Smart Healthcare for Disease Diagnosis and Prevention, pp. 115-123, 2020.
    [CrossRef] [Google Scholar] [Publisher Link]
  9. Dwip Narayan Mukherjee, Saradindu Panda, and Bansibadan Maji, “Design and Optimization of Reversible Logic Based Magnitude Comparator Using Gate Diffusion Input Technique,” IETE Journal of Research, vol. 69, no. 6, pp. 3625-3637, 2023.
    [CrossRef] [Google Scholar] [Publisher Link]
  10. Seyedeh Fatemeh Deymad, Nabiollah Shiri, and Farshad Pesaran, “High-Efficient Reversible Full Adder Realized by Dynamic Threshold-Based Gate Diffusion Input Logics,” Microelectronics Journal, vol. 142, 2023.
    [CrossRef] [Google Scholar] [Publisher Link]
  11. D. N. Mukherjee, S. Panda, and B. Maji, “A Novel Design of 12-bit Digital Comparator Using Multiplexer for High-Speed Application in 32-nm CMOS Technology,” IETE Journal of Research, vol. 68, no. 2, pp. 1350-1357, 2019.
    [CrossRef] [Google Scholar] [Publisher Link]
  12. Madhina Basha, and V.N. Lakshmana Kumar, “Transistor Implementation of Reversible Comparator Circuit Using Low Power Technique,” International Journal of Computer Science and Information Technologies, vol. 3, no. 3, pp. 4447-4452, 2012.
    [Google Scholar] [Publisher Link]
  13. Chetan Vudadha et al., “Design of Prefix-Based Optimal Reversible Comparator,” 2012 IEEE Computer Society Annual Symposium on VLSI, Amherst, MA, USA, pp. 201-206, 2012.
    [CrossRef] [Google Scholar] [Publisher Link]
  14. Ri-gui Zhou et al., “Optimization Approaches for Designing a Novel 4-bit Reversible Comparator,” International Journal of Theoretical Physics, vol. 52, pp. 559-575, 2013.
    [CrossRef] [Google Scholar] [Publisher Link]
  15. Hari Mohan Gaur, Ashutosh Kumar Singh, and Umesh Ghanekar, “In-Depth Comparative Analysis of Reversible Gates for Designing Logic Circuits,” Procedia Computer Science, vol. 125, pp. 810-817, 2018.
    [CrossRef] [Google Scholar] [Publisher Link]
  16. Harsh Pallav Govind Rao, and Shiva Dwivedi, “Logical Unit Design using Reversible HSG1 Gate and Its Application in ALU Design,” 2020 11th International Conference on Computing, Communication and Networking Technologies (ICCCNT), Kharagpur, India, pp. 1-6, 2020.
    [CrossRef] [Google Scholar] [Publisher Link]
  17. Mozammel H. A Khan, “Design of Reversible Synchronous Sequential Circuits Using Pseudo Reed-Muller Expressions,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 22, no. 11, pp. 2278-2286, 2014.
    [CrossRef] [Google Scholar] [Publisher Link]
  18. D.P. Vasudevan et al., “Reversible-Logic Design with Online Testability,” IEEE Transactions on Instrumentation and Measurement, vol. 55, no. 2, pp. 406-414, 2006.
    [CrossRef] [Google Scholar] [Publisher Link]
  19. Mariam Zomorodi Moghadam, and Keivan Navi, “Ultra-Area-Efficient Reversible Multiplier,” Microelectronics Journal, vol. 43, no. 6, pp. 377-385, 2012.
    [CrossRef] [Google Scholar] [Publisher Link]
  20. Md. Selim Al Mamun, and David Menville, “Quantum Cost Optimization for Reversible Sequential Circuit,” International Journal of Advanced Computer Science and Applications, vol. 4, no. 12, pp. 15-21, 2013.
    [CrossRef] [Google Scholar] [Publisher Link]
  21. Lafifa Jamal et al., “An Efficient Approach to Design a Reversible Control Unit of a Processor,” Sustainable Computing: Informatics and Systems, vol. 3, no. 4, pp. 286-294, 2013.
    [CrossRef] [Google Scholar] [Publisher Link]
  22. A. Kamaraj, and P. Marichamy, “Design of Integrated Reversible Fault-Tolerant Arithmetic and Logic Unit,” Microprocessors and Microsystems, vol. 69, pp. 16-23, 2019.
    [CrossRef] [Google Scholar] [Publisher Link]
  23. K. Nishanth Rao et al., “A Novel Energy Efficient 4-bit Vedic Multiplier using Modified GDI approach at 32 nm Technology,” Heliyon, vol. 10, no. 10, pp. 1-15, 2024.
    [CrossRef] [Google Scholar] [Publisher Link]
  24. Hafiz Md. Hasan Babu et al., “Approach to Design a Compact Reversible Low Power Binary Comparator,” IET Computers & Digital Techniques, vol. 8, no. 3, pp. 109-162, 2014.
    [CrossRef] [Google Scholar] [Publisher Link]
  25. A.N Nagamani, Desik Rengarajan, and Vinod K Agrawal, “An Optimized Design of Reversible Magnitude and Signed Comparator,” 2016 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC), Hong Kong, China, pp. 108-111, 2016.
    [CrossRef] [Google Scholar] [Publisher Link]
  26. Oleg Golubitsky, and Dmitri Maslov, “A Study of Optimal 4-Bit Reversible Toffoli Circuits and Their Synthesis,” IEEE Transactions on Computers, vol. 61, no. 9, pp. 1341-1353, 2012.
    [CrossRef] [Google Scholar] [Publisher Link]
  27. Jebashini Ponnian et al., “A New Systematic GDI Circuit Synthesis Using Mux Based Decomposition Algorithm and Binary Decision Diagram for Low Power ASIC Circuit Design,” Microelectronics Journal, vol. 108, 2021.
    [CrossRef] [Google Scholar] [Publisher Link]
  28. Somashekhar Malipatil, Avinash Gour, and Vikas Maheshwari, “Fault Tolerant Reversible Full Adder Design Using Gate Diffusion Input,” 2020 International Conference on Smart Technologies in Computing, Electrical and Electronics (ICSTCEE), Bengaluru, India, pp. 120-123, 2020.
    [CrossRef] [Google Scholar] [Publisher Link]
  29. Majety Naveenkumar, “Novel Design of Reversible MUX and DEMUX using GDI Technique,” International Journal of Advances in Applied Sciences, vol. 4, no. 3, pp. 103-108, 2015.
    [CrossRef] [Google Scholar] [Publisher Link]
  30. B. Sai kumar, A. Akilandeswari, and EMG Subramanian, “Design of 4:1 Multiplexer using Gate Diffusion Input Technique and Comparison of Delay and Power Performance with CMOS Logic,” 2022 14th International Conference on Mathematics, Actuarial Science, Computer Science and Statistics (MACS), Karachi, Pakistan, pp. 1-5, 2022.
    [CrossRef] [Google Scholar] [Publisher Link]
  31. Dwip Narayan Mukherjee, Saradindu Panda, and Bansibadan Maji, “Performance Evaluation of Digital Comparator Using Different Logic Styles,” IETE Journal of Research, vol. 64, no. 3, pp. 422-429, 2018.
    [CrossRef] [Google Scholar] [Publisher Link]
  32. C. Kalamani et al., “Design of Encoder and Decoder Using Reversible Logic Gates,” Measurement: Sensors, vol. 31, pp. 1-12, 2024.
    [CrossRef] [Google Scholar] [Publisher Link]
  33. Himanshu Thapliyal, Nagarajan Ranganathan, and Ryan Ferreira, “Design of a Comparator Tree based on Reversible Logic,” 10th IEEE International Conference on Nanotechnology, Ilsan, Korea (South), pp. 1113-1116, 2010.
    [CrossRef] [Google Scholar] [Publisher Link]
  34. Lihui Ni et al., “Using New Designed NLG gate for the Realization of Four-bit Reversible Numerical comparator,” 2010 International Conference on Educational and Network Technology, Qinhuangdao, pp. 254-258, 2010.
    [CrossRef] [Google Scholar] [Publisher Link]
  35. Tarlochan Singh, and Chakshu Goel, “An Optimal Approach to Design 4-bit Reversible Power Efficient Comparator,” International Journal of Engineering Research & Technology, vol. 5, no. 3, pp. 166-171, 2016.
    [Google Scholar] [Publisher Link]